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Feed through and synchronize FIFO status signals

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This commit is contained in:
Alex Forencich 2015-05-12 19:12:23 -07:00
parent 22124ec361
commit ec95a6055d
6 changed files with 186 additions and 6 deletions
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52
rtl/eth_mac_10g_fifo.v
View File

@ -76,8 +76,14 @@ module eth_mac_10g_fifo #
/*
* Status
*/
output wire tx_fifo_overflow,
output wire tx_fifo_bad_frame,
output wire tx_fifo_good_frame,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire rx_fifo_overflow,
output wire rx_fifo_bad_frame,
output wire rx_fifo_good_frame,
/*
* Configuration
@ -98,6 +104,40 @@ wire rx_fifo_axis_tvalid;
wire rx_fifo_axis_tlast;
wire rx_fifo_axis_tuser;
// synchronize FIFO status signals into logic clock domain (only required for RX FIFO)
wire rx_fifo_overflow_int;
wire rx_fifo_bad_frame_int;
wire rx_fifo_good_frame_int;
reg [2:0] rx_sync_reg_1 = 0;
reg [2:0] rx_sync_reg_2 = 0;
reg [2:0] rx_sync_reg_3 = 0;
reg [2:0] rx_sync_reg_4 = 0;
assign rx_fifo_overflow = rx_sync_reg_3[0] ^ rx_sync_reg_4[0];
assign rx_fifo_bad_frame = rx_sync_reg_3[1] ^ rx_sync_reg_4[1];
assign rx_fifo_good_frame = rx_sync_reg_3[2] ^ rx_sync_reg_4[2];
always @(posedge rx_clk or posedge rx_rst) begin
if (rx_rst) begin
rx_sync_reg_1 <= 0;
end else begin
rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_fifo_good_frame_int, rx_fifo_bad_frame_int, rx_fifo_overflow_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
rx_sync_reg_2 <= 0;
rx_sync_reg_3 <= 0;
rx_sync_reg_4 <= 0;
end else begin
rx_sync_reg_2 <= rx_sync_reg_1;
rx_sync_reg_3 <= rx_sync_reg_2;
rx_sync_reg_4 <= rx_sync_reg_3;
end
end
eth_mac_10g #(
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
@ -150,7 +190,11 @@ tx_fifo (
.output_axis_tkeep(tx_fifo_axis_tkeep),
.output_axis_tvalid(tx_fifo_axis_tvalid),
.output_axis_tready(tx_fifo_axis_tready),
.output_axis_tlast(tx_fifo_axis_tlast)
.output_axis_tlast(tx_fifo_axis_tlast),
// Status
.overflow(tx_fifo_overflow),
.bad_frame(tx_fifo_bad_frame),
.good_frame(tx_fifo_good_frame)
);
assign tx_fifo_axis_tuser = 1'b0;
@ -177,7 +221,11 @@ rx_fifo (
.output_axis_tkeep(rx_axis_tkeep),
.output_axis_tvalid(rx_axis_tvalid),
.output_axis_tready(rx_axis_tready),
.output_axis_tlast(rx_axis_tlast)
.output_axis_tlast(rx_axis_tlast),
// Status
.overflow(rx_fifo_overflow_int),
.bad_frame(rx_fifo_bad_frame_int),
.good_frame(rx_fifo_good_frame_int)
);
assign rx_axis_tuser = 1'b0;

52
rtl/eth_mac_1g_fifo.v
View File

@ -75,8 +75,14 @@ module eth_mac_1g_fifo #
/*
* Status
*/
output wire tx_fifo_overflow,
output wire tx_fifo_bad_frame,
output wire tx_fifo_good_frame,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire rx_fifo_overflow,
output wire rx_fifo_bad_frame,
output wire rx_fifo_good_frame,
/*
* Configuration
@ -95,6 +101,40 @@ wire rx_fifo_axis_tvalid;
wire rx_fifo_axis_tlast;
wire rx_fifo_axis_tuser;
// synchronize FIFO status signals into logic clock domain (only required for RX FIFO)
wire rx_fifo_overflow_int;
wire rx_fifo_bad_frame_int;
wire rx_fifo_good_frame_int;
reg [2:0] rx_sync_reg_1 = 0;
reg [2:0] rx_sync_reg_2 = 0;
reg [2:0] rx_sync_reg_3 = 0;
reg [2:0] rx_sync_reg_4 = 0;
assign rx_fifo_overflow = rx_sync_reg_3[0] ^ rx_sync_reg_4[0];
assign rx_fifo_bad_frame = rx_sync_reg_3[1] ^ rx_sync_reg_4[1];
assign rx_fifo_good_frame = rx_sync_reg_3[2] ^ rx_sync_reg_4[2];
always @(posedge rx_clk or posedge rx_rst) begin
if (rx_rst) begin
rx_sync_reg_1 <= 0;
end else begin
rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_fifo_good_frame_int, rx_fifo_bad_frame_int, rx_fifo_overflow_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
rx_sync_reg_2 <= 0;
rx_sync_reg_3 <= 0;
rx_sync_reg_4 <= 0;
end else begin
rx_sync_reg_2 <= rx_sync_reg_1;
rx_sync_reg_3 <= rx_sync_reg_2;
rx_sync_reg_4 <= rx_sync_reg_3;
end
end
eth_mac_1g #(
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
@ -144,7 +184,11 @@ tx_fifo (
.output_axis_tdata(tx_fifo_axis_tdata),
.output_axis_tvalid(tx_fifo_axis_tvalid),
.output_axis_tready(tx_fifo_axis_tready),
.output_axis_tlast(tx_fifo_axis_tlast)
.output_axis_tlast(tx_fifo_axis_tlast),
// Status
.overflow(tx_fifo_overflow),
.bad_frame(tx_fifo_bad_frame),
.good_frame(tx_fifo_good_frame)
);
assign tx_fifo_axis_tuser = 1'b0;
@ -169,7 +213,11 @@ rx_fifo (
.output_axis_tdata(rx_axis_tdata),
.output_axis_tvalid(rx_axis_tvalid),
.output_axis_tready(rx_axis_tready),
.output_axis_tlast(rx_axis_tlast)
.output_axis_tlast(rx_axis_tlast),
// Status
.overflow(rx_fifo_overflow_int),
.bad_frame(rx_fifo_bad_frame_int),
.good_frame(rx_fifo_good_frame_int)
);
assign rx_axis_tuser = 1'b0;

24
tb/test_eth_mac_10g_fifo.py
View File

@ -91,6 +91,12 @@ def dut_eth_mac_1g(clk,
rx_error_bad_frame,
rx_error_bad_fcs,
rx_fifo_overflow,
rx_fifo_bad_frame,
rx_fifo_good_frame,
tx_fifo_overflow,
tx_fifo_bad_frame,
tx_fifo_good_frame,
ifg_delay):
@ -128,8 +134,14 @@ def dut_eth_mac_1g(clk,
xgmii_txd=xgmii_txd,
xgmii_txc=xgmii_txc,
tx_fifo_overflow=tx_fifo_overflow,
tx_fifo_bad_frame=tx_fifo_bad_frame,
tx_fifo_good_frame=tx_fifo_good_frame,
rx_error_bad_frame=rx_error_bad_frame,
rx_error_bad_fcs=rx_error_bad_fcs,
rx_fifo_overflow=rx_fifo_overflow,
rx_fifo_bad_frame=rx_fifo_bad_frame,
rx_fifo_good_frame=rx_fifo_good_frame,
ifg_delay=ifg_delay)
@ -172,8 +184,14 @@ def bench():
rx_axis_tuser = Signal(bool(0))
xgmii_txd = Signal(intbv(0x0707070707070707)[64:])
xgmii_txc = Signal(intbv(0xff)[8:])
tx_fifo_overflow = Signal(bool(0))
tx_fifo_bad_frame = Signal(bool(0))
tx_fifo_good_frame = Signal(bool(0))
rx_error_bad_frame = Signal(bool(0))
rx_error_bad_fcs = Signal(bool(0))
rx_fifo_overflow = Signal(bool(0))
rx_fifo_bad_frame = Signal(bool(0))
rx_fifo_good_frame = Signal(bool(0))
# sources and sinks
xgmii_source_queue = Queue()
@ -251,8 +269,14 @@ def bench():
xgmii_txd,
xgmii_txc,
tx_fifo_overflow,
tx_fifo_bad_frame,
tx_fifo_good_frame,
rx_error_bad_frame,
rx_error_bad_fcs,
rx_fifo_overflow,
rx_fifo_bad_frame,
rx_fifo_good_frame,
ifg_delay)

20
tb/test_eth_mac_10g_fifo.v
View File

@ -68,8 +68,14 @@ wire rx_axis_tlast;
wire rx_axis_tuser;
wire [63:0] xgmii_txd;
wire [7:0] xgmii_txc;
wire tx_fifo_overflow;
wire tx_fifo_bad_frame;
wire tx_fifo_good_frame;
wire rx_error_bad_frame;
wire rx_error_bad_fcs;
wire rx_fifo_overflow;
wire rx_fifo_bad_frame;
wire rx_fifo_good_frame;
initial begin
// myhdl integration
@ -99,8 +105,14 @@ initial begin
rx_axis_tuser,
xgmii_txd,
xgmii_txc,
tx_fifo_overflow,
tx_fifo_bad_frame,
tx_fifo_good_frame,
rx_error_bad_frame,
rx_error_bad_fcs);
rx_error_bad_fcs,
rx_fifo_overflow,
rx_fifo_bad_frame,
rx_fifo_good_frame);
// dump file
$dumpfile("test_eth_mac_10g_fifo.lxt");
@ -137,8 +149,14 @@ UUT (
.xgmii_rxc(xgmii_rxc),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.tx_fifo_overflow(tx_fifo_overflow),
.tx_fifo_bad_frame(tx_fifo_bad_frame),
.tx_fifo_good_frame(tx_fifo_good_frame),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.rx_fifo_overflow(rx_fifo_overflow),
.rx_fifo_bad_frame(rx_fifo_bad_frame),
.rx_fifo_good_frame(rx_fifo_good_frame),
.ifg_delay(ifg_delay)
);

24
tb/test_eth_mac_1g_fifo.py
View File

@ -84,6 +84,12 @@ def dut_eth_mac_1g(clk,
rx_error_bad_frame,
rx_error_bad_fcs,
tx_fifo_overflow,
tx_fifo_bad_frame,
tx_fifo_good_frame,
rx_fifo_overflow,
rx_fifo_bad_frame,
rx_fifo_good_frame,
ifg_delay):
@ -121,8 +127,14 @@ def dut_eth_mac_1g(clk,
gmii_tx_en=gmii_tx_en,
gmii_tx_er=gmii_tx_er,
tx_fifo_overflow=tx_fifo_overflow,
tx_fifo_bad_frame=tx_fifo_bad_frame,
tx_fifo_good_frame=tx_fifo_good_frame,
rx_error_bad_frame=rx_error_bad_frame,
rx_error_bad_fcs=rx_error_bad_fcs,
rx_fifo_overflow=rx_fifo_overflow,
rx_fifo_bad_frame=rx_fifo_bad_frame,
rx_fifo_good_frame=rx_fifo_good_frame,
ifg_delay=ifg_delay)
@ -164,8 +176,14 @@ def bench():
gmii_txd = Signal(intbv(0)[8:])
gmii_tx_en = Signal(bool(0))
gmii_tx_er = Signal(bool(0))
tx_fifo_overflow = Signal(bool(0))
tx_fifo_bad_frame = Signal(bool(0))
tx_fifo_good_frame = Signal(bool(0))
rx_error_bad_frame = Signal(bool(0))
rx_error_bad_fcs = Signal(bool(0))
rx_fifo_overflow = Signal(bool(0))
rx_fifo_bad_frame = Signal(bool(0))
rx_fifo_good_frame = Signal(bool(0))
# sources and sinks
gmii_source_queue = Queue()
@ -243,8 +261,14 @@ def bench():
gmii_tx_en,
gmii_tx_er,
tx_fifo_overflow,
tx_fifo_bad_frame,
tx_fifo_good_frame,
rx_error_bad_frame,
rx_error_bad_fcs,
rx_fifo_overflow,
rx_fifo_bad_frame,
rx_fifo_good_frame,
ifg_delay)

20
tb/test_eth_mac_1g_fifo.v
View File

@ -67,8 +67,14 @@ wire rx_axis_tuser;
wire [7:0] gmii_txd;
wire gmii_tx_en;
wire gmii_tx_er;
wire tx_fifo_overflow;
wire tx_fifo_bad_frame;
wire tx_fifo_good_frame;
wire rx_error_bad_frame;
wire rx_error_bad_fcs;
wire rx_fifo_overflow;
wire rx_fifo_bad_frame;
wire rx_fifo_good_frame;
initial begin
// myhdl integration
@ -98,8 +104,14 @@ initial begin
gmii_txd,
gmii_tx_en,
gmii_tx_er,
tx_fifo_overflow,
tx_fifo_bad_frame,
tx_fifo_good_frame,
rx_error_bad_frame,
rx_error_bad_fcs);
rx_error_bad_fcs,
rx_fifo_overflow,
rx_fifo_bad_frame,
rx_fifo_good_frame);
// dump file
$dumpfile("test_eth_mac_1g_fifo.lxt");
@ -135,8 +147,14 @@ UUT (
.gmii_txd(gmii_txd),
.gmii_tx_en(gmii_tx_en),
.gmii_tx_er(gmii_tx_er),
.tx_fifo_overflow(tx_fifo_overflow),
.tx_fifo_bad_frame(tx_fifo_bad_frame),
.tx_fifo_good_frame(tx_fifo_good_frame),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.rx_fifo_overflow(rx_fifo_overflow),
.rx_fifo_bad_frame(rx_fifo_bad_frame),
.rx_fifo_good_frame(rx_fifo_good_frame),
.ifg_delay(ifg_delay)
);