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https://github.com/alexforencich/verilog-ethernet.git
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Separate locked status from fast-forward mode in PTP period output module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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@ -118,6 +118,7 @@ reg [15:0] ts_96_fns_ovf_reg = 0, ts_96_fns_ovf_next;
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reg locked_reg = 1'b0, locked_next;
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reg error_reg = 1'b0, error_next;
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reg ffwd_reg = 1'b0, ffwd_next;
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reg level_reg = 1'b0, level_next;
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reg output_reg = 1'b0, output_next;
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@ -144,6 +145,7 @@ always @* begin
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locked_next = locked_reg;
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error_next = error_reg;
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ffwd_next = ffwd_reg;
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level_next = level_reg;
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output_next = output_reg;
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@ -163,9 +165,10 @@ always @* begin
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next_rise_fns_next = start_fns_reg;
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end
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locked_next = 1'b0;
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level_next = 1'b0;
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ffwd_next = 1'b1;
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output_next = 1'b0;
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state_next = STATE_UPDATE_FALL_1;
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level_next = 1'b0;
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state_next = STATE_WAIT_EDGE;
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end
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STATE_UPDATE_RISE_1: begin
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// set next rise time to next rise time plus period
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@ -208,19 +211,26 @@ always @* begin
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state_next = STATE_WAIT_EDGE;
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end
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STATE_WAIT_EDGE: begin
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if ((time_s_reg > next_rise_s_reg) || (time_s_reg == next_rise_s_reg && {time_ns_reg, time_fns_reg} > {next_rise_ns_reg, next_rise_fns_reg})) begin
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if ((!level_reg || ffwd_reg) && ((time_s_reg > next_rise_s_reg) || (time_s_reg == next_rise_s_reg && {time_ns_reg, time_fns_reg} > {next_rise_ns_reg, next_rise_fns_reg}))) begin
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// rising edge
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level_next = 1'b1;
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output_next = enable && locked_reg;
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state_next = STATE_UPDATE_RISE_1;
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end else if ((time_s_reg > next_fall_s_reg) || (time_s_reg == next_fall_s_reg && {time_ns_reg, time_fns_reg} > {next_fall_ns_reg, next_fall_fns_reg})) begin
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if (ffwd_reg) begin
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output_next = 1'b0;
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level_next = 1'b0;
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state_next = STATE_UPDATE_RISE_1;
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end else begin
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locked_next = 1'b1;
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error_next = 1'b0;
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output_next = enable;
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level_next = 1'b1;
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state_next = STATE_UPDATE_FALL_1;
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end
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end else if (level_reg && ((time_s_reg > next_fall_s_reg) || (time_s_reg == next_fall_s_reg && {time_ns_reg, time_fns_reg} > {next_fall_ns_reg, next_fall_fns_reg}))) begin
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// falling edge
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level_next = 1'b0;
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output_next = 1'b0;
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state_next = STATE_UPDATE_FALL_1;
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level_next = 1'b0;
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state_next = STATE_UPDATE_RISE_1;
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end else begin
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locked_next = locked_reg || level_reg;
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error_next = error_reg && !(locked_reg || level_reg);
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ffwd_next = 1'b0;
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state_next = STATE_WAIT_EDGE;
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end
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end
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@ -285,6 +295,7 @@ always @(posedge clk) begin
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locked_reg <= locked_next;
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error_reg <= error_next;
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ffwd_reg <= ffwd_next;
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level_reg <= level_next;
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output_reg <= output_next;
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