mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-28 07:03:08 +08:00
Rework termination character handling in XGMII RX modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
parent
12744433de
commit
f37bb1fc8d
@ -111,10 +111,9 @@ reg [1:0] state_reg = STATE_IDLE, state_next;
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// datapath control signals
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reg reset_crc;
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reg [3:0] last_cycle_tkeep_reg = 4'd0, last_cycle_tkeep_next;
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reg [DATA_WIDTH-1:0] xgmii_rxd_masked = {DATA_WIDTH{1'b0}};
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reg [CTRL_WIDTH-1:0] xgmii_term = {CTRL_WIDTH{1'b0}};
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reg [1:0] term_lane_reg = 0, term_lane_d0_reg = 0;
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reg term_present_reg = 1'b0;
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reg framing_error_reg = 1'b0;
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reg [DATA_WIDTH-1:0] xgmii_rxd_d0 = {DATA_WIDTH{1'b0}};
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reg [DATA_WIDTH-1:0] xgmii_rxd_d1 = {DATA_WIDTH{1'b0}};
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@ -176,63 +175,11 @@ eth_crc (
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.state_out(crc_next)
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);
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// Mask input data
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integer j;
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always @* begin
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for (j = 0; j < 4; j = j + 1) begin
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xgmii_rxd_masked[j*8 +: 8] = xgmii_rxc[j] ? 8'd0 : xgmii_rxd[j*8 +: 8];
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xgmii_term[j] = xgmii_rxc[j] && (xgmii_rxd[j*8 +: 8] == XGMII_TERM);
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end
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end
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// detect control characters
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reg [3:0] detect_term = 4'd0;
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reg [3:0] detect_term_save;
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integer i;
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// mask errors to within packet
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reg [3:0] control_masked;
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reg [3:0] tkeep_mask;
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always @* begin
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casez (detect_term)
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4'b0000: begin
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control_masked = xgmii_rxc_d0;
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tkeep_mask = 4'b1111;
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end
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4'bzzz1: begin
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control_masked = 0;
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tkeep_mask = 4'b0000;
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end
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4'bzz10: begin
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control_masked = xgmii_rxc_d0[0];
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tkeep_mask = 4'b0001;
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end
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4'bz100: begin
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control_masked = xgmii_rxc_d0[1:0];
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tkeep_mask = 4'b0011;
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end
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4'b1000: begin
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control_masked = xgmii_rxc_d0[2:0];
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tkeep_mask = 4'b0111;
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end
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default: begin
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control_masked = xgmii_rxc_d0;
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tkeep_mask = 4'b1111;
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end
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endcase
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end
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always @* begin
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state_next = STATE_IDLE;
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reset_crc = 1'b0;
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last_cycle_tkeep_next = last_cycle_tkeep_reg;
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m_axis_tdata_next = {DATA_WIDTH{1'b0}};
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m_axis_tkeep_next = {KEEP_WIDTH{1'b1}};
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m_axis_tvalid_next = 1'b0;
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@ -251,7 +198,7 @@ always @* begin
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if (xgmii_start_d2 && cfg_rx_enable) begin
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// start condition
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if (control_masked) begin
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if (framing_error_reg) begin
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// control or error characters in first data word
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m_axis_tdata_next = {DATA_WIDTH{1'b0}};
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m_axis_tkeep_next = 4'h1;
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@ -284,25 +231,20 @@ always @* begin
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m_axis_tlast_next = 1'b0;
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m_axis_tuser_next[0] = 1'b0;
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last_cycle_tkeep_next = tkeep_mask;
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if (detect_term) begin
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reset_crc = 1'b1;
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end
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if (control_masked) begin
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if (framing_error_reg) begin
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// control or error characters in packet
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m_axis_tlast_next = 1'b1;
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m_axis_tuser_next[0] = 1'b1;
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error_bad_frame_next = 1'b1;
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reset_crc = 1'b1;
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state_next = STATE_IDLE;
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end else if (detect_term) begin
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if (detect_term[0]) begin
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end else if (term_present_reg) begin
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reset_crc = 1'b1;
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if (term_lane_reg == 0) begin
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// end this cycle
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m_axis_tkeep_next = 4'b1111;
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m_axis_tlast_next = 1'b1;
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if (detect_term[0] && crc_valid_save[3]) begin
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if (term_lane_reg == 0 && crc_valid_save[3]) begin
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// CRC valid
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end else begin
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m_axis_tuser_next[0] = 1'b1;
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@ -321,16 +263,16 @@ always @* begin
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STATE_LAST: begin
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// last cycle of packet
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m_axis_tdata_next = xgmii_rxd_d2;
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m_axis_tkeep_next = last_cycle_tkeep_reg;
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m_axis_tkeep_next = {KEEP_WIDTH{1'b1}} >> (CTRL_WIDTH-term_lane_d0_reg);
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m_axis_tvalid_next = 1'b1;
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m_axis_tlast_next = 1'b1;
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m_axis_tuser_next[0] = 1'b0;
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reset_crc = 1'b1;
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if ((detect_term_save[1] && crc_valid_save[0]) ||
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(detect_term_save[2] && crc_valid_save[1]) ||
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(detect_term_save[3] && crc_valid_save[2])) begin
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if ((term_lane_d0_reg == 1 && crc_valid_save[0]) ||
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(term_lane_d0_reg == 2 && crc_valid_save[1]) ||
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(term_lane_d0_reg == 3 && crc_valid_save[2])) begin
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// CRC valid
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end else begin
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m_axis_tuser_next[0] = 1'b1;
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@ -343,6 +285,8 @@ always @* begin
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endcase
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end
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integer i;
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always @(posedge clk) begin
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state_reg <= state_next;
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@ -356,10 +300,19 @@ always @(posedge clk) begin
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error_bad_frame_reg <= error_bad_frame_next;
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error_bad_fcs_reg <= error_bad_fcs_next;
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last_cycle_tkeep_reg <= last_cycle_tkeep_next;
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term_lane_reg <= 0;
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term_present_reg <= 1'b0;
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framing_error_reg <= xgmii_rxc != 0;
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detect_term <= xgmii_term;
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detect_term_save <= detect_term;
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for (i = CTRL_WIDTH-1; i >= 0; i = i - 1) begin
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if (xgmii_rxc[i] && (xgmii_rxd[i*8 +: 8] == XGMII_TERM)) begin
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term_lane_reg <= i;
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term_present_reg <= 1'b1;
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framing_error_reg <= (xgmii_rxc & ({CTRL_WIDTH{1'b1}} >> (CTRL_WIDTH-i))) != 0;
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end
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end
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term_lane_d0_reg <= term_lane_reg;
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if (reset_crc) begin
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crc_state <= 32'hFFFFFFFF;
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@ -369,7 +322,9 @@ always @(posedge clk) begin
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crc_valid_save <= crc_valid;
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xgmii_rxd_d0 <= xgmii_rxd_masked;
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for (i = 0; i < CTRL_WIDTH; i = i + 1) begin
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xgmii_rxd_d0[i*8 +: 8] <= xgmii_rxc[i] ? 8'd0 : xgmii_rxd[i*8 +: 8];
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end
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xgmii_rxc_d0 <= xgmii_rxc;
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xgmii_rxd_d1 <= xgmii_rxd_d0;
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xgmii_rxd_d2 <= xgmii_rxd_d1;
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@ -112,8 +112,6 @@ reg [1:0] state_reg = STATE_IDLE, state_next;
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// datapath control signals
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reg reset_crc;
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reg [7:0] last_cycle_tkeep_reg = 8'd0, last_cycle_tkeep_next;
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reg lanes_swapped = 1'b0;
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reg [31:0] swap_rxd = 32'd0;
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reg [3:0] swap_rxc = 4'd0;
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@ -121,6 +119,9 @@ reg [3:0] swap_rxc_term = 4'd0;
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reg [DATA_WIDTH-1:0] xgmii_rxd_masked = {DATA_WIDTH{1'b0}};
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reg [CTRL_WIDTH-1:0] xgmii_term = {CTRL_WIDTH{1'b0}};
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reg [2:0] term_lane_reg = 0, term_lane_d0_reg = 0;
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reg term_present_reg = 1'b0;
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reg framing_error_reg = 1'b0;
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reg [DATA_WIDTH-1:0] xgmii_rxd_d0 = {DATA_WIDTH{1'b0}};
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reg [DATA_WIDTH-1:0] xgmii_rxd_d1 = {DATA_WIDTH{1'b0}};
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@ -197,69 +198,11 @@ always @* begin
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end
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end
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// detect control characters
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reg [7:0] detect_term = 8'd0;
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reg [7:0] detect_term_save = 8'd0;
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integer i;
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// mask errors to within packet
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reg [7:0] control_masked;
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reg [7:0] tkeep_mask;
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always @* begin
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casez (detect_term)
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8'b00000000: begin
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control_masked = xgmii_rxc_d0;
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tkeep_mask = 8'b11111111;
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end
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8'bzzzzzzz1: begin
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control_masked = 0;
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tkeep_mask = 8'b00000000;
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end
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8'bzzzzzz10: begin
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control_masked = xgmii_rxc_d0[0];
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tkeep_mask = 8'b00000001;
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end
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8'bzzzzz100: begin
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control_masked = xgmii_rxc_d0[1:0];
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tkeep_mask = 8'b00000011;
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end
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8'bzzzz1000: begin
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control_masked = xgmii_rxc_d0[2:0];
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tkeep_mask = 8'b00000111;
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end
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8'bzzz10000: begin
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control_masked = xgmii_rxc_d0[3:0];
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tkeep_mask = 8'b00001111;
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end
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8'bzz100000: begin
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control_masked = xgmii_rxc_d0[4:0];
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tkeep_mask = 8'b00011111;
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end
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8'bz1000000: begin
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control_masked = xgmii_rxc_d0[5:0];
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tkeep_mask = 8'b00111111;
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end
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8'b10000000: begin
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control_masked = xgmii_rxc_d0[6:0];
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tkeep_mask = 8'b01111111;
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end
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default: begin
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control_masked = xgmii_rxc_d0;
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tkeep_mask = 8'b11111111;
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end
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endcase
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end
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always @* begin
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state_next = STATE_IDLE;
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reset_crc = 1'b0;
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last_cycle_tkeep_next = last_cycle_tkeep_reg;
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m_axis_tdata_next = {DATA_WIDTH{1'b0}};
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m_axis_tkeep_next = {KEEP_WIDTH{1'b1}};
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m_axis_tvalid_next = 1'b0;
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@ -282,7 +225,7 @@ always @* begin
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m_axis_tuser_next[1 +: PTP_TS_WIDTH] = (PTP_TS_WIDTH != 96 || ptp_ts_borrow_reg) ? ptp_ts_reg : ptp_ts_adj_reg;
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end
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if (control_masked) begin
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if (framing_error_reg) begin
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// control or error characters in first data word
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m_axis_tdata_next = {DATA_WIDTH{1'b0}};
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m_axis_tkeep_next = 8'h01;
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@ -307,29 +250,24 @@ always @* begin
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m_axis_tlast_next = 1'b0;
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m_axis_tuser_next[0] = 1'b0;
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last_cycle_tkeep_next = {4'b0000, tkeep_mask[7:4]};
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if (detect_term) begin
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reset_crc = 1'b1;
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end
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if (control_masked) begin
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if (framing_error_reg) begin
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// control or error characters in packet
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m_axis_tlast_next = 1'b1;
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m_axis_tuser_next[0] = 1'b1;
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error_bad_frame_next = 1'b1;
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reset_crc = 1'b1;
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state_next = STATE_IDLE;
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end else if (detect_term) begin
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if (detect_term[4:0]) begin
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end else if (term_present_reg) begin
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reset_crc = 1'b1;
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if (term_lane_reg <= 4) begin
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// end this cycle
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m_axis_tkeep_next = {tkeep_mask[3:0], 4'b1111};
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m_axis_tkeep_next = {KEEP_WIDTH{1'b1}} >> (CTRL_WIDTH-4-term_lane_reg);
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m_axis_tlast_next = 1'b1;
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if ((detect_term[0] && crc_valid_save[7]) ||
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(detect_term[1] && crc_valid[0]) ||
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(detect_term[2] && crc_valid[1]) ||
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(detect_term[3] && crc_valid[2]) ||
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(detect_term[4] && crc_valid[3])) begin
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if ((term_lane_reg == 0 && crc_valid_save[7]) ||
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(term_lane_reg == 1 && crc_valid[0]) ||
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(term_lane_reg == 2 && crc_valid[1]) ||
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(term_lane_reg == 3 && crc_valid[2]) ||
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(term_lane_reg == 4 && crc_valid[3])) begin
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// CRC valid
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end else begin
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m_axis_tuser_next[0] = 1'b1;
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@ -348,16 +286,16 @@ always @* begin
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STATE_LAST: begin
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// last cycle of packet
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m_axis_tdata_next = xgmii_rxd_d1;
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m_axis_tkeep_next = last_cycle_tkeep_reg;
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m_axis_tkeep_next = {KEEP_WIDTH{1'b1}} >> (CTRL_WIDTH+4-term_lane_d0_reg);
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m_axis_tvalid_next = 1'b1;
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m_axis_tlast_next = 1'b1;
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m_axis_tuser_next[0] = 1'b0;
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reset_crc = 1'b1;
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if ((detect_term_save[5] && crc_valid_save[4]) ||
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(detect_term_save[6] && crc_valid_save[5]) ||
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(detect_term_save[7] && crc_valid_save[6])) begin
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if ((term_lane_d0_reg == 5 && crc_valid_save[4]) ||
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(term_lane_d0_reg == 6 && crc_valid_save[5]) ||
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(term_lane_d0_reg == 7 && crc_valid_save[6])) begin
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// CRC valid
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end else begin
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m_axis_tuser_next[0] = 1'b1;
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@ -367,7 +305,7 @@ always @* begin
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if (xgmii_start_d1) begin
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// start condition
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if (control_masked) begin
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if (framing_error_reg) begin
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// control or error characters in first data word
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m_axis_tdata_next = {DATA_WIDTH{1'b0}};
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m_axis_tkeep_next = 8'h01;
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@ -387,6 +325,8 @@ always @* begin
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endcase
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end
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integer i;
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always @(posedge clk) begin
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state_reg <= state_next;
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@ -400,10 +340,6 @@ always @(posedge clk) begin
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error_bad_frame_reg <= error_bad_frame_next;
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error_bad_fcs_reg <= error_bad_fcs_next;
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last_cycle_tkeep_reg <= last_cycle_tkeep_next;
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detect_term_save <= detect_term;
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swap_rxd <= xgmii_rxd_masked[63:32];
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swap_rxc <= xgmii_rxc[7:4];
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swap_rxc_term <= xgmii_term[7:4];
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@ -419,15 +355,47 @@ always @(posedge clk) begin
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ptp_ts_adj_reg[95:48] <= ptp_ts_reg[95:48] + 1;
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end
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if (xgmii_rxc[0] && xgmii_rxd[7:0] == XGMII_START) begin
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if (lanes_swapped) begin
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xgmii_rxd_d0 <= {xgmii_rxd_masked[31:0], swap_rxd};
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xgmii_rxc_d0 <= {xgmii_rxc[3:0], swap_rxc};
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term_lane_reg <= 0;
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term_present_reg <= 1'b0;
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framing_error_reg <= {xgmii_rxc[3:0], swap_rxc} != 0;
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for (i = CTRL_WIDTH-1; i >= 0; i = i - 1) begin
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if ({xgmii_term[3:0], swap_rxc_term} & (1 << i)) begin
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term_lane_reg <= i;
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term_present_reg <= 1'b1;
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framing_error_reg <= ({xgmii_rxc[3:0], swap_rxc} & ({CTRL_WIDTH{1'b1}} >> (CTRL_WIDTH-i))) != 0;
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lanes_swapped <= 1'b0;
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start_packet_reg <= 2'b01;
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end
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end
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end else begin
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xgmii_rxd_d0 <= xgmii_rxd_masked;
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xgmii_rxc_d0 <= xgmii_rxc;
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xgmii_start_d0 <= 1'b1;
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term_lane_reg <= 0;
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term_present_reg <= 1'b0;
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framing_error_reg <= xgmii_rxc != 0;
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detect_term <= xgmii_term;
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for (i = CTRL_WIDTH-1; i >= 0; i = i - 1) begin
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if (xgmii_rxc[i] && (xgmii_rxd[i*8 +: 8] == XGMII_TERM)) begin
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term_lane_reg <= i;
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term_present_reg <= 1'b1;
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framing_error_reg <= (xgmii_rxc & ({CTRL_WIDTH{1'b1}} >> (CTRL_WIDTH-i))) != 0;
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||||
lanes_swapped <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
term_lane_d0_reg <= term_lane_reg;
|
||||
|
||||
if (xgmii_rxc[0] && xgmii_rxd[7:0] == XGMII_START) begin
|
||||
lanes_swapped <= 1'b0;
|
||||
start_packet_reg <= 2'b01;
|
||||
|
||||
xgmii_start_d0 <= 1'b1;
|
||||
|
||||
if (PTP_TS_WIDTH == 96) begin
|
||||
ptp_ts_reg[45:0] <= ptp_ts[45:0] + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS);
|
||||
@ -438,29 +406,15 @@ always @(posedge clk) begin
|
||||
end else if (xgmii_rxc[4] && xgmii_rxd[39:32] == XGMII_START) begin
|
||||
lanes_swapped <= 1'b1;
|
||||
start_packet_reg <= 2'b10;
|
||||
xgmii_rxd_d0 <= {xgmii_rxd_masked[31:0], swap_rxd};
|
||||
xgmii_rxc_d0 <= {xgmii_rxc[3:0], swap_rxc};
|
||||
|
||||
xgmii_start_swap <= 1'b1;
|
||||
|
||||
detect_term <= {xgmii_term[3:0], swap_rxc_term};
|
||||
|
||||
if (PTP_TS_WIDTH == 96) begin
|
||||
ptp_ts_reg[45:0] <= ptp_ts[45:0] + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1);
|
||||
ptp_ts_reg[95:48] <= ptp_ts[95:48];
|
||||
end else begin
|
||||
ptp_ts_reg <= ptp_ts + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1);
|
||||
end
|
||||
end else if (lanes_swapped) begin
|
||||
xgmii_rxd_d0 <= {xgmii_rxd_masked[31:0], swap_rxd};
|
||||
xgmii_rxc_d0 <= {xgmii_rxc[3:0], swap_rxc};
|
||||
|
||||
detect_term <= {xgmii_term[3:0], swap_rxc_term};
|
||||
end else begin
|
||||
xgmii_rxd_d0 <= xgmii_rxd_masked;
|
||||
xgmii_rxc_d0 <= xgmii_rxc;
|
||||
|
||||
detect_term <= xgmii_term;
|
||||
end
|
||||
|
||||
if (reset_crc) begin
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user