FPGA/verilog-ethernet
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Fix widths

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This commit is contained in:
Alex Forencich 2019-03-14 14:44:00 -07:00
parent 013e88253e
commit fb4abb6b39
3 changed files with 6 additions and 6 deletions
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4
rtl/arp_eth_tx_64.v
View File

@ -282,13 +282,13 @@ always @(posedge clk) begin
end
// output datapath logic
reg [64:0] m_eth_payload_axis_tdata_reg = 64'd0;
reg [63:0] m_eth_payload_axis_tdata_reg = 64'd0;
reg [7:0] m_eth_payload_axis_tkeep_reg = 8'd0;
reg m_eth_payload_axis_tvalid_reg = 1'b0, m_eth_payload_axis_tvalid_next;
reg m_eth_payload_axis_tlast_reg = 1'b0;
reg m_eth_payload_axis_tuser_reg = 1'b0;
reg [64:0] temp_m_eth_payload_axis_tdata_reg = 64'd0;
reg [63:0] temp_m_eth_payload_axis_tdata_reg = 64'd0;
reg [7:0] temp_m_eth_payload_axis_tkeep_reg = 8'd0;
reg temp_m_eth_payload_axis_tvalid_reg = 1'b0, temp_m_eth_payload_axis_tvalid_next;
reg temp_m_eth_payload_axis_tlast_reg = 1'b0;

4
rtl/eth_axis_rx_64.v
View File

@ -326,13 +326,13 @@ always @(posedge clk) begin
end
// output datapath logic
reg [64:0] m_eth_payload_axis_tdata_reg = 64'd0;
reg [63:0] m_eth_payload_axis_tdata_reg = 64'd0;
reg [7:0] m_eth_payload_axis_tkeep_reg = 8'd0;
reg m_eth_payload_axis_tvalid_reg = 1'b0, m_eth_payload_axis_tvalid_next;
reg m_eth_payload_axis_tlast_reg = 1'b0;
reg m_eth_payload_axis_tuser_reg = 1'b0;
reg [64:0] temp_m_eth_payload_axis_tdata_reg = 64'd0;
reg [63:0] temp_m_eth_payload_axis_tdata_reg = 64'd0;
reg [7:0] temp_m_eth_payload_axis_tkeep_reg = 8'd0;
reg temp_m_eth_payload_axis_tvalid_reg = 1'b0, temp_m_eth_payload_axis_tvalid_next;
reg temp_m_eth_payload_axis_tlast_reg = 1'b0;

4
rtl/ip_eth_tx_64.v
View File

@ -550,13 +550,13 @@ always @(posedge clk) begin
end
// output datapath logic
reg [64:0] m_eth_payload_axis_tdata_reg = 64'd0;
reg [63:0] m_eth_payload_axis_tdata_reg = 64'd0;
reg [7:0] m_eth_payload_axis_tkeep_reg = 8'd0;
reg m_eth_payload_axis_tvalid_reg = 1'b0, m_eth_payload_axis_tvalid_next;
reg m_eth_payload_axis_tlast_reg = 1'b0;
reg m_eth_payload_axis_tuser_reg = 1'b0;
reg [64:0] temp_m_eth_payload_axis_tdata_reg = 64'd0;
reg [63:0] temp_m_eth_payload_axis_tdata_reg = 64'd0;
reg [7:0] temp_m_eth_payload_axis_tkeep_reg = 8'd0;
reg temp_m_eth_payload_axis_tvalid_reg = 1'b0, temp_m_eth_payload_axis_tvalid_next;
reg temp_m_eth_payload_axis_tlast_reg = 1'b0;