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Remove length fields from ARP transmit module

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This commit is contained in:
Alex Forencich 2014-09-17 12:36:56 -07:00
parent 33c044e035
commit fdb31878e9
7 changed files with 6 additions and 54 deletions
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12
rtl/arp_eth_tx.v
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@ -44,8 +44,6 @@ module arp_eth_tx
input wire [15:0] input_eth_type,
input wire [15:0] input_arp_htype,
input wire [15:0] input_arp_ptype,
input wire [7:0] input_arp_hlen,
input wire [7:0] input_arp_plen,
input wire [15:0] input_arp_oper,
input wire [47:0] input_arp_sha,
input wire [31:0] input_arp_spa,
@ -117,8 +115,6 @@ reg [47:0] output_eth_src_mac_reg = 0;
reg [15:0] output_eth_type_reg = 0;
reg [15:0] arp_htype_reg = 0;
reg [15:0] arp_ptype_reg = 0;
reg [7:0] arp_hlen_reg = 0;
reg [7:0] arp_plen_reg = 0;
reg [15:0] arp_oper_reg = 0;
reg [47:0] arp_sha_reg = 0;
reg [31:0] arp_spa_reg = 0;
@ -188,8 +184,8 @@ always @* begin
8'h01: write_hdr_data = arp_htype_reg[ 7: 0];
8'h02: write_hdr_data = arp_ptype_reg[15: 8];
8'h03: write_hdr_data = arp_ptype_reg[ 7: 0];
8'h04: write_hdr_data = arp_hlen_reg;
8'h05: write_hdr_data = arp_plen_reg;
8'h04: write_hdr_data = 6; // hlen
8'h05: write_hdr_data = 4; // plen
8'h06: write_hdr_data = arp_oper_reg[15: 8];
8'h07: write_hdr_data = arp_oper_reg[ 7: 0];
8'h08: write_hdr_data = arp_sha_reg[47:40];
@ -243,8 +239,6 @@ always @(posedge clk or posedge rst) begin
output_eth_type_reg <= 0;
arp_htype_reg <= 0;
arp_ptype_reg <= 0;
arp_hlen_reg <= 0;
arp_plen_reg <= 0;
arp_oper_reg <= 0;
arp_sha_reg <= 0;
arp_spa_reg <= 0;
@ -289,8 +283,6 @@ always @(posedge clk or posedge rst) begin
output_eth_type_reg <= input_eth_type;
arp_htype_reg <= input_arp_htype;
arp_ptype_reg <= input_arp_ptype;
arp_hlen_reg <= input_arp_hlen;
arp_plen_reg <= input_arp_plen;
arp_oper_reg <= input_arp_oper;
arp_sha_reg <= input_arp_sha;
arp_spa_reg <= input_arp_spa;

12
rtl/arp_eth_tx_64.v
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@ -44,8 +44,6 @@ module arp_eth_tx_64
input wire [15:0] input_eth_type,
input wire [15:0] input_arp_htype,
input wire [15:0] input_arp_ptype,
input wire [7:0] input_arp_hlen,
input wire [7:0] input_arp_plen,
input wire [15:0] input_arp_oper,
input wire [47:0] input_arp_sha,
input wire [31:0] input_arp_spa,
@ -119,8 +117,6 @@ reg [47:0] output_eth_src_mac_reg = 0;
reg [15:0] output_eth_type_reg = 0;
reg [15:0] arp_htype_reg = 0;
reg [15:0] arp_ptype_reg = 0;
reg [7:0] arp_hlen_reg = 0;
reg [7:0] arp_plen_reg = 0;
reg [15:0] arp_oper_reg = 0;
reg [47:0] arp_sha_reg = 0;
reg [31:0] arp_spa_reg = 0;
@ -178,8 +174,8 @@ always @* begin
write_hdr_data[15: 8] = input_arp_htype[ 7: 0];
write_hdr_data[23:16] = input_arp_ptype[15: 8];
write_hdr_data[31:24] = input_arp_ptype[ 7: 0];
write_hdr_data[39:32] = input_arp_hlen;
write_hdr_data[47:40] = input_arp_plen;
write_hdr_data[39:32] = 6; // hlen
write_hdr_data[47:40] = 4; // plen
write_hdr_data[55:48] = input_arp_oper[15: 8];
write_hdr_data[63:56] = input_arp_oper[ 7: 0];
write_hdr_keep = 8'hff;
@ -260,8 +256,6 @@ always @(posedge clk or posedge rst) begin
output_eth_type_reg <= 0;
arp_htype_reg <= 0;
arp_ptype_reg <= 0;
arp_hlen_reg <= 0;
arp_plen_reg <= 0;
arp_oper_reg <= 0;
arp_sha_reg <= 0;
arp_spa_reg <= 0;
@ -307,8 +301,6 @@ always @(posedge clk or posedge rst) begin
output_eth_type_reg <= input_eth_type;
arp_htype_reg <= input_arp_htype;
arp_ptype_reg <= input_arp_ptype;
arp_hlen_reg <= input_arp_hlen;
arp_plen_reg <= input_arp_plen;
arp_oper_reg <= input_arp_oper;
arp_sha_reg <= input_arp_sha;
arp_spa_reg <= input_arp_spa;

4
tb/arp_ep.py
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@ -158,8 +158,8 @@ def ARPFrameSource(clk, rst,
eth_type=None,
arp_htype=None,
arp_ptype=None,
arp_hlen=None,
arp_plen=None,
arp_hlen=Signal(intbv(0)[8:]),
arp_plen=Signal(intbv(0)[8:]),
arp_oper=None,
arp_sha=None,
arp_spa=None,

10
tb/test_arp_eth_tx.py
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@ -53,8 +53,6 @@ def dut_arp_eth_tx(clk,
input_eth_type,
input_arp_htype,
input_arp_ptype,
input_arp_hlen,
input_arp_plen,
input_arp_oper,
input_arp_sha,
input_arp_spa,
@ -88,8 +86,6 @@ def dut_arp_eth_tx(clk,
input_eth_type=input_eth_type,
input_arp_htype=input_arp_htype,
input_arp_ptype=input_arp_ptype,
input_arp_hlen=input_arp_hlen,
input_arp_plen=input_arp_plen,
input_arp_oper=input_arp_oper,
input_arp_sha=input_arp_sha,
input_arp_spa=input_arp_spa,
@ -122,8 +118,6 @@ def bench():
input_eth_type = Signal(intbv(0)[16:])
input_arp_htype = Signal(intbv(0)[16:])
input_arp_ptype = Signal(intbv(0)[16:])
input_arp_hlen = Signal(intbv(0)[8:])
input_arp_plen = Signal(intbv(0)[8:])
input_arp_oper = Signal(intbv(0)[16:])
input_arp_sha = Signal(intbv(0)[48:])
input_arp_spa = Signal(intbv(0)[32:])
@ -159,8 +153,6 @@ def bench():
eth_type=input_eth_type,
arp_htype=input_arp_htype,
arp_ptype=input_arp_ptype,
arp_hlen=input_arp_hlen,
arp_plen=input_arp_plen,
arp_oper=input_arp_oper,
arp_sha=input_arp_sha,
arp_spa=input_arp_spa,
@ -198,8 +190,6 @@ def bench():
input_eth_type,
input_arp_htype,
input_arp_ptype,
input_arp_hlen,
input_arp_plen,
input_arp_oper,
input_arp_sha,
input_arp_spa,

6
tb/test_arp_eth_tx.v
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@ -39,8 +39,6 @@ reg [47:0] input_eth_src_mac = 0;
reg [15:0] input_eth_type = 0;
reg [15:0] input_arp_htype = 0;
reg [15:0] input_arp_ptype = 0;
reg [7:0] input_arp_hlen = 0;
reg [7:0] input_arp_plen = 0;
reg [15:0] input_arp_oper = 0;
reg [47:0] input_arp_sha = 0;
reg [31:0] input_arp_spa = 0;
@ -72,8 +70,6 @@ initial begin
input_eth_type,
input_arp_htype,
input_arp_ptype,
input_arp_hlen,
input_arp_plen,
input_arp_oper,
input_arp_sha,
input_arp_spa,
@ -109,8 +105,6 @@ UUT (
.input_eth_type(input_eth_type),
.input_arp_htype(input_arp_htype),
.input_arp_ptype(input_arp_ptype),
.input_arp_hlen(input_arp_hlen),
.input_arp_plen(input_arp_plen),
.input_arp_oper(input_arp_oper),
.input_arp_sha(input_arp_sha),
.input_arp_spa(input_arp_spa),

10
tb/test_arp_eth_tx_64.py
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@ -53,8 +53,6 @@ def dut_arp_eth_tx_64(clk,
input_eth_type,
input_arp_htype,
input_arp_ptype,
input_arp_hlen,
input_arp_plen,
input_arp_oper,
input_arp_sha,
input_arp_spa,
@ -89,8 +87,6 @@ def dut_arp_eth_tx_64(clk,
input_eth_type=input_eth_type,
input_arp_htype=input_arp_htype,
input_arp_ptype=input_arp_ptype,
input_arp_hlen=input_arp_hlen,
input_arp_plen=input_arp_plen,
input_arp_oper=input_arp_oper,
input_arp_sha=input_arp_sha,
input_arp_spa=input_arp_spa,
@ -124,8 +120,6 @@ def bench():
input_eth_type = Signal(intbv(0)[16:])
input_arp_htype = Signal(intbv(0)[16:])
input_arp_ptype = Signal(intbv(0)[16:])
input_arp_hlen = Signal(intbv(0)[8:])
input_arp_plen = Signal(intbv(0)[8:])
input_arp_oper = Signal(intbv(0)[16:])
input_arp_sha = Signal(intbv(0)[48:])
input_arp_spa = Signal(intbv(0)[32:])
@ -162,8 +156,6 @@ def bench():
eth_type=input_eth_type,
arp_htype=input_arp_htype,
arp_ptype=input_arp_ptype,
arp_hlen=input_arp_hlen,
arp_plen=input_arp_plen,
arp_oper=input_arp_oper,
arp_sha=input_arp_sha,
arp_spa=input_arp_spa,
@ -202,8 +194,6 @@ def bench():
input_eth_type,
input_arp_htype,
input_arp_ptype,
input_arp_hlen,
input_arp_plen,
input_arp_oper,
input_arp_sha,
input_arp_spa,

6
tb/test_arp_eth_tx_64.v
View File

@ -39,8 +39,6 @@ reg [47:0] input_eth_src_mac = 0;
reg [15:0] input_eth_type = 0;
reg [15:0] input_arp_htype = 0;
reg [15:0] input_arp_ptype = 0;
reg [7:0] input_arp_hlen = 0;
reg [7:0] input_arp_plen = 0;
reg [15:0] input_arp_oper = 0;
reg [47:0] input_arp_sha = 0;
reg [31:0] input_arp_spa = 0;
@ -73,8 +71,6 @@ initial begin
input_eth_type,
input_arp_htype,
input_arp_ptype,
input_arp_hlen,
input_arp_plen,
input_arp_oper,
input_arp_sha,
input_arp_spa,
@ -111,8 +107,6 @@ UUT (
.input_eth_type(input_eth_type),
.input_arp_htype(input_arp_htype),
.input_arp_ptype(input_arp_ptype),
.input_arp_hlen(input_arp_hlen),
.input_arp_plen(input_arp_plen),
.input_arp_oper(input_arp_oper),
.input_arp_sha(input_arp_sha),
.input_arp_spa(input_arp_spa),