FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-14 06:43:18 +08:00
Code Issues Projects Releases Wiki Activity

Update readme

Browse Source
This commit is contained in:
Alex Forencich 2018-07-02 16:25:29 -07:00
parent 3063bba54b
commit ffc63e4b0d
1 changed files with 11 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
README.md
View File

@ -44,6 +44,15 @@ Supports power of two depths only.
Basic frame-based asynchronous FIFO with parametrizable data width and depth. Basic frame-based asynchronous FIFO with parametrizable data width and depth.
Supports power of two depths only. Supports power of two depths only.
### axis_cobs_decode
Consistent Overhead Byte Stuffing (COBS) decoder. Fixed 8 bit width.
### axis_cobs_encode
Consistent Overhead Byte Stuffing (COBS) encoder. Fixed 8 bit width.
Configurable zero insertion.
### axis_crosspoint module ### axis_crosspoint module
Basic crosspoint switch. tready signal not supported. Parametrizable data Basic crosspoint switch. tready signal not supported. Parametrizable data
@ -180,6 +189,8 @@ Parametrizable priority encoder.
axis_arb_mux_4.v : 4 port arbitrated multiplexer axis_arb_mux_4.v : 4 port arbitrated multiplexer
axis_async_fifo.v : Asynchronous FIFO axis_async_fifo.v : Asynchronous FIFO
axis_async_frame_fifo.v : Asynchronous frame FIFO axis_async_frame_fifo.v : Asynchronous frame FIFO
axis_cobs_decode.v : COBS decoder
axis_cobs_encode.v : COBS encoder
axis_crosspoint.py : Crosspoint switch generator axis_crosspoint.py : Crosspoint switch generator
axis_crosspoint_4x4.v : 4x4 crosspoint switch axis_crosspoint_4x4.v : 4x4 crosspoint switch
axis_demux.py : Demultiplexer generator axis_demux.py : Demultiplexer generator