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Author SHA1 Message Date
Alex Forencich
baac5f8d81 Reorganize PTP timestamp capture logic; determine PTP clock step size from PTP time instead of parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-02-12 17:29:31 -08:00
Alex Forencich
839fe8cbbe Add ptp_td_rel2tod module for timestamp reconstruction 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-02-11 13:01:29 -08:00
Alex Forencich
c5d069444a Move alternate offset switch near the end of the current second to extend reconstruction range for timestamps in the past 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-02-11 13:01:03 -08:00
Alex Forencich
870cebb798 Clean up PTP parameters on MACs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-02-11 13:00:37 -08:00
Alex Forencich
ae17f7db00 Remove extraneous scaleb(-9) in set_ts_tod_ns in ptp_td so that the seconds field can be set correctly 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-02-09 15:12:19 -08:00
Alex Forencich
22abe6cacb merged changes in axis 2024-02-05 17:30:40 -08:00
Alex Forencich
0ac15c6872 Split out and pipeline relative timestamp LSB increment in PTP TD leaf clock 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-02-05 16:22:02 -08:00
Alex Forencich
eb0f01f276 Rework MAC TX error handling to streamline logic; pad errored frames to avoid generating runt frames 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-29 18:33:14 -08:00
Alex Forencich
e24f887009 Add TX underrun and error tests 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-29 16:16:11 -08:00
Alex Forencich
915f4c21ff Cleanup RGMII PHY IF, fix TX error indication 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-29 16:10:58 -08:00
Alex Forencich
b784f23c71 Fix wait end state in GMII TX 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-28 21:31:55 -08:00
Alex Forencich
13c1872a42 Clean up XGMII symbol generation 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-28 20:36:06 -08:00
Alex Forencich
10b6d2f5bc Force AXIS RAM switch output FIFO into distributed RAM 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-28 16:38:38 -08:00
Alex Forencich
0d3f5fbbc4 Handle framing errors in payload state in XGMII RX module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-28 14:53:15 -08:00
Alex Forencich
685df9317f Unconditionally transfer out XGMII data in XGMII RX modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-28 14:43:59 -08:00
Alex Forencich
8074748564 Move timestamp capture into payload state in XGMII RX module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-28 14:43:18 -08:00
Alex Forencich
f37bb1fc8d Rework termination character handling in XGMII RX modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-27 14:06:32 -08:00
Alex Forencich
c6ecd770e7 Fix spurious multi-driven net issue in axis_ram_switch when S_ID_WIDTH = 0 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-26 12:35:27 -08:00
Alex Forencich
12744433de merged changes in axis 2024-01-17 15:10:47 -08:00
Alex Forencich
a29282cdda Remove stall cycle in axis_arb_mux 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-17 15:08:57 -08:00
Alex Forencich
e493c6cdb4 Fix FIFO output pause logic 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-17 12:17:11 -08:00
Alex Forencich
b4d09cbbdf More extensive overhaul of the PTP period output module to improve resource consumption and parallelize computation 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-16 17:01:03 -08:00
Alex Forencich
f313fafc70 Separate locked status from fast-forward mode in PTP period output module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-15 22:55:50 -08:00
Alex Forencich
f400372b1c Add missing assign to frame_min_count_reg in axis_xgmii_tx_32 module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-14 20:51:14 -08:00
Alex Forencich
b22db1d2d2 Add CRC state registers where possible to 10G/25G MAC modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-14 19:17:00 -08:00
Alex Forencich
f08eb74666 Optimize block type decoding in 10G PHY RX to reduce fanin 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-14 16:14:57 -08:00
Alex Forencich
74936e83c5 Add register on PRBS checker output in 10G PHY RX to improve timing performance 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-14 16:10:20 -08:00
Alex Forencich
a05d1a4550 Rename Arista_7132LB to DCS7132LB 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-14 15:45:38 -08:00
Alex Forencich
dce0c92a57 Rework PHC to register shared adder outputs for improved timing performance 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-12-02 00:53:02 -08:00
Alex Forencich
dd97924714 Prevent stale data frim being used to sync leaf clock 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-12-01 22:05:53 -08:00
Alex Forencich
f0c47db509 Improve tolerance of sample point synchronization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-12-01 22:03:14 -08:00
Alex Forencich
a2294c56a5 Rewrite gain scheduling 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-12-01 22:02:40 -08:00
Alex Forencich
89ee44d410 Add test for PCIe spread spectrum clocking 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-12-01 22:02:09 -08:00
Alex Forencich
36cf9c9b06 Remove unnecessary shadow valid registers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-12-01 14:03:55 -08:00
Alex Forencich
be0d9b7b88 Improve handling of instance name mangling 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-12-01 13:37:25 -08:00
Alex Forencich
5560fa2b32 Fix timestamp capture/sync logic 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-30 14:05:16 -08:00
Alex Forencich
16cd84123d Add user_sma_clk pins to VCU108 and VCU118 constraints files 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-29 13:58:22 -08:00
Alex Forencich
7f9fed6f84 Update readme 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-10 16:56:42 -08:00
Alex Forencich
3535e53746 Add example design for Alveo U55C and Alveo U55N/Varium C1100 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-10 15:40:14 -08:00
Alex Forencich
fe5f6aa3f5 Merge AU50 into Alveo example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-10 15:32:38 -08:00
Alex Forencich
de818ad621 Merge AU280 into Alveo example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-10 15:30:37 -08:00
Alex Forencich
58732ebeb3 Rework Alveo parametrization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-10 15:25:38 -08:00
Alex Forencich
0986d1e901 Rework 7132 parametrization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-08 13:36:21 -08:00
Alex Forencich
1b29a88b18 Rename AU200 to Alveo 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-08 11:50:50 -08:00
Alex Forencich
bd8e8e5b20 Add PTP time distribution components 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-07 13:07:15 -08:00
Alex Forencich
009560f583 Use latest version of cocotbext-eth 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-07 12:18:46 -08:00
Alex Forencich
01badce3a1 Remove unnecessary resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-01 18:30:32 -07:00
Alex Forencich
49513b45d4 Merge AU200, AU250, and VCU1525 designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-10-12 22:51:07 -07:00
Alex Forencich
e84da8dbfb Update HTG-9200 readmes 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-26 23:12:52 -07:00
Alex Forencich
b5d1fadb7e Add makefiles for VU13P variant of HTG-9200 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-26 15:07:16 -07:00