FPGA/verilog-ethernet
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4 Commits

Author SHA1 Message Date
Alex Forencich
48cbe43fa7 Update Vivado makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 18:48:34 -07:00
Alex Forencich
7a0e88ffea Update vivado.mk 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-13 14:57:46 -08:00
Alex Forencich
97182ccf4e Update vivado.mk 2021-06-23 20:07:29 -07:00
Alex Forencich
9a8ba2f0f2 Add ZCU102 example design 2020-09-18 00:15:21 -07:00