FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-28 07:03:08 +08:00
Code Issues Projects Releases Wiki Activity
1,202 Commits 1 Branch 0 Tags
Commit Graph

353 Commits

Author SHA1 Message Date
Alex Forencich
baac5f8d81 Reorganize PTP timestamp capture logic; determine PTP clock step size from PTP time instead of parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-02-12 17:29:31 -08:00
Alex Forencich
839fe8cbbe Add ptp_td_rel2tod module for timestamp reconstruction 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-02-11 13:01:29 -08:00
Alex Forencich
c5d069444a Move alternate offset switch near the end of the current second to extend reconstruction range for timestamps in the past 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-02-11 13:01:03 -08:00
Alex Forencich
870cebb798 Clean up PTP parameters on MACs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-02-11 13:00:37 -08:00
Alex Forencich
0ac15c6872 Split out and pipeline relative timestamp LSB increment in PTP TD leaf clock 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-02-05 16:22:02 -08:00
Alex Forencich
eb0f01f276 Rework MAC TX error handling to streamline logic; pad errored frames to avoid generating runt frames 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-29 18:33:14 -08:00
Alex Forencich
915f4c21ff Cleanup RGMII PHY IF, fix TX error indication 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-29 16:10:58 -08:00
Alex Forencich
b784f23c71 Fix wait end state in GMII TX 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-28 21:31:55 -08:00
Alex Forencich
13c1872a42 Clean up XGMII symbol generation 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-28 20:36:06 -08:00
Alex Forencich
0d3f5fbbc4 Handle framing errors in payload state in XGMII RX module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-28 14:53:15 -08:00
Alex Forencich
685df9317f Unconditionally transfer out XGMII data in XGMII RX modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-28 14:43:59 -08:00
Alex Forencich
8074748564 Move timestamp capture into payload state in XGMII RX module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-28 14:43:18 -08:00
Alex Forencich
f37bb1fc8d Rework termination character handling in XGMII RX modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-27 14:06:32 -08:00
Alex Forencich
b4d09cbbdf More extensive overhaul of the PTP period output module to improve resource consumption and parallelize computation 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-16 17:01:03 -08:00
Alex Forencich
f313fafc70 Separate locked status from fast-forward mode in PTP period output module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-15 22:55:50 -08:00
Alex Forencich
f400372b1c Add missing assign to frame_min_count_reg in axis_xgmii_tx_32 module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-14 20:51:14 -08:00
Alex Forencich
b22db1d2d2 Add CRC state registers where possible to 10G/25G MAC modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-14 19:17:00 -08:00
Alex Forencich
f08eb74666 Optimize block type decoding in 10G PHY RX to reduce fanin 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-14 16:14:57 -08:00
Alex Forencich
74936e83c5 Add register on PRBS checker output in 10G PHY RX to improve timing performance 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-14 16:10:20 -08:00
Alex Forencich
dce0c92a57 Rework PHC to register shared adder outputs for improved timing performance 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-12-02 00:53:02 -08:00
Alex Forencich
dd97924714 Prevent stale data frim being used to sync leaf clock 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-12-01 22:05:53 -08:00
Alex Forencich
f0c47db509 Improve tolerance of sample point synchronization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-12-01 22:03:14 -08:00
Alex Forencich
a2294c56a5 Rewrite gain scheduling 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-12-01 22:02:40 -08:00
Alex Forencich
36cf9c9b06 Remove unnecessary shadow valid registers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-12-01 14:03:55 -08:00
Alex Forencich
5560fa2b32 Fix timestamp capture/sync logic 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-30 14:05:16 -08:00
Alex Forencich
bd8e8e5b20 Add PTP time distribution components 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-07 13:07:15 -08:00
Alex Forencich
01badce3a1 Remove unnecessary resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-01 18:30:32 -07:00
Alex Forencich
5ff1e17a29 Add missing assign to frame_min_count_reg in axis_baser_tx_64 module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-24 13:35:29 -07:00
Alex Forencich
90e6dfc638 Use phase detector in PTP CDC module for coarse period tuning, use 9 LSBs of timestamp for fine sync to avoid rollover corrections, reduce FNS comparison width to 4 bits 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-23 14:58:44 -07:00
Alex Forencich
f9ae6da8bd Improve PTP CDC module testbench 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-23 14:33:14 -07:00
Alex Forencich
5a37442706 Merge FNS registers into NS registers in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-22 22:52:59 -07:00
Alex Forencich
b0a4d75fd9 Remove extraneous code 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-22 01:08:01 -07:00
Alex Forencich
4a32c86f07 Match integrator width to period register width in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-22 01:07:43 -07:00
Alex Forencich
cf441f004d Rename source sync signals in PTP CDC module for consistency 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-22 01:07:12 -07:00
Alex Forencich
4b1f48ab5b Parameter clean-up in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-21 16:34:05 -07:00
Alex Forencich
aad30d09a1 Make FNS_WIDTH an internal parameter in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-21 16:30:29 -07:00
Alex Forencich
98b4fbb56d Remove USE_SAMPLE_CLOCK parameter in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-18 16:58:02 -07:00
Alex Forencich
fa05d4ff3c Add TX and RX enable inputs to MACs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-24 01:24:33 -07:00
Alex Forencich
20c542051d Use cfg prefix for configuration signals 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-22 17:14:52 -07:00
Alex Forencich
70cc19ff15 Add MAC control layer to core 1G and 10G MAC modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-23 22:24:42 -07:00
Alex Forencich
ba5a883433 Add pause/PFC modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-23 16:31:33 -07:00
Alex Forencich
6d5cda5986 Add MAC control layer modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-22 00:47:15 -07:00
Alex Forencich
2858aaaef7 Add TX PTP timestamp enable bit in tuser 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-17 10:58:40 -07:00
Alex Forencich
9665df8a44 Fix PTP timestamping in 1G MAC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-08 01:41:14 -07:00
Alex Forencich
1f0b6a625c PTP parameter clean-up 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-06 16:46:32 -07:00
Alex Forencich
9dafc3aaee Use internal BYTE_LANES parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-06 16:28:08 -07:00
Alex Forencich
f705646e3e Pull out header size as a parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-29 15:48:39 -07:00
Alex Forencich
77adf30dad Add missing serdes_rx_reset_req output to 10G MAC+PHY modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-22 17:36:01 -08:00
Alex Forencich
450765187e Update lfsr.v 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-15 12:36:03 -08:00
Alex Forencich
cb1dc8fb15 Optimize FCS verification in 10G/25G MAC modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-13 15:47:30 -08:00