FPGA/verilog-ethernet
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236 Commits

Author SHA1 Message Date
Alex Forencich
baac5f8d81 Reorganize PTP timestamp capture logic; determine PTP clock step size from PTP time instead of parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-02-12 17:29:31 -08:00
Alex Forencich
839fe8cbbe Add ptp_td_rel2tod module for timestamp reconstruction 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-02-11 13:01:29 -08:00
Alex Forencich
c5d069444a Move alternate offset switch near the end of the current second to extend reconstruction range for timestamps in the past 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-02-11 13:01:03 -08:00
Alex Forencich
870cebb798 Clean up PTP parameters on MACs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-02-11 13:00:37 -08:00
Alex Forencich
ae17f7db00 Remove extraneous scaleb(-9) in set_ts_tod_ns in ptp_td so that the seconds field can be set correctly 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-02-09 15:12:19 -08:00
Alex Forencich
e24f887009 Add TX underrun and error tests 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-29 16:16:11 -08:00
Alex Forencich
89ee44d410 Add test for PCIe spread spectrum clocking 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-12-01 22:02:09 -08:00
Alex Forencich
bd8e8e5b20 Add PTP time distribution components 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-07 13:07:15 -08:00
Alex Forencich
009560f583 Use latest version of cocotbext-eth 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-07 12:18:46 -08:00
Alex Forencich
a9e3d3cae8 Wait longer to ensure PTP CDC module has fully stabilized in MAC testbenches 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-23 14:52:48 -07:00
Alex Forencich
f9ae6da8bd Improve PTP CDC module testbench 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-23 14:33:14 -07:00
Alex Forencich
aad30d09a1 Make FNS_WIDTH an internal parameter in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-21 16:30:29 -07:00
Alex Forencich
98b4fbb56d Remove USE_SAMPLE_CLOCK parameter in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-18 16:58:02 -07:00
Alex Forencich
060e55b915 Wait for correct PTP CDC instance to lock 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-18 16:39:30 -07:00
Alex Forencich
fa05d4ff3c Add TX and RX enable inputs to MACs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-24 01:24:33 -07:00
Alex Forencich
20c542051d Use cfg prefix for configuration signals 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-22 17:14:52 -07:00
Alex Forencich
02ce168c63 Improve PTP-related tests 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-24 01:01:54 -07:00
Alex Forencich
fa173f93e5 Avoid testbench reset during alignment test 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-24 00:57:43 -07:00
Alex Forencich
70cc19ff15 Add MAC control layer to core 1G and 10G MAC modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-23 22:24:42 -07:00
Alex Forencich
ba5a883433 Add pause/PFC modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-23 16:31:33 -07:00
Alex Forencich
6d5cda5986 Add MAC control layer modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-22 00:47:15 -07:00
Alex Forencich
2858aaaef7 Add TX PTP timestamp enable bit in tuser 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-17 10:58:40 -07:00
Alex Forencich
905e6c6358 Add PTP timestamping tests for 1G MAC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-08 01:41:35 -07:00
Alex Forencich
1f0b6a625c PTP parameter clean-up 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-06 16:46:32 -07:00
Alex Forencich
9159425cd8 Use correct payload lengths 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-29 22:18:50 -07:00
Alex Forencich
c65161e696 Remove recursively-expanded macros for module parameters in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-17 16:04:16 -08:00
Alex Forencich
ab0c382123 Rework parameter handling in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-29 21:03:16 -08:00
Alex Forencich
5e528e0057 Update FIFO PIPELINE_OUTPUT to RAM_PIPELINE 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 23:56:11 -07:00
Alex Forencich
c1e947dc3d Timing optimization of PTP modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-22 22:57:44 -07:00
Alex Forencich
a5934dae60 Add PTP timestamping tests to MACs and related modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 23:21:42 -07:00
Alex Forencich
6f2d581d62 Add output pipeline to PTP clock CDC module 2022-03-27 23:47:14 -07:00
Alex Forencich
945f22fd33 Add output pipeline to PTP clock module 2022-03-27 23:46:49 -07:00
Alex Forencich
0f2db26a8e Simplify logic in PTP clock module 2022-03-16 19:01:00 -07:00
Alex Forencich
23fb9d0bd8 Remove deprecated assignments 2022-03-16 18:43:36 -07:00
Alex Forencich
1f80696b55 Use start_soon instead of fork 2021-12-10 18:19:11 -08:00
Alex Forencich
8bd6c8ea34 Remove some lint 2021-11-07 18:23:13 -08:00
Alex Forencich
32d99b4dd9 Use constants from cocotbext-eth 2021-11-07 18:21:06 -08:00
Alex Forencich
625c48c59c Add transceiver reset watchdog 2021-10-17 20:19:04 -07:00
Alex Forencich
a540e50e1c Fix XGMII to BASE-R control character mapping 2021-10-15 16:14:02 -07:00
Alex Forencich
a539a76ec4 Add cocotb testbenches for 10G MAC+PHY modules 2021-10-15 01:37:10 -07:00
Alex Forencich
e7dddc0dfd Add cocotb testbenches for AXI stream BASE-R TX and RX modules 2021-10-15 01:08:14 -07:00
Alex Forencich
8b95b33bab Add cocotb testbench for 10G PHY 2021-10-15 01:07:26 -07:00
Alex Forencich
2d9f01f9fe Add cocotb testbenches for XGMII BASE-R encoder and decoder modules 2021-10-15 01:06:57 -07:00
Alex Forencich
c0e2eb2b07 Add BASE-R serdes models for cocotb 2021-10-15 00:36:56 -07:00
Alex Forencich
c44e447db5 Transfer PTP information in tuser 2021-09-01 15:56:00 -07:00
Alex Forencich
77938fa422 Update MAC modules for changes in FIFO modules 2021-08-26 00:55:12 -07:00
Alex Forencich
5415c41c41 Remove string parameters 2021-06-02 17:50:26 -07:00
Alex Forencich
5e1329a992 Rework PHY bitslip timing 2021-05-05 00:35:43 -07:00
Alex Forencich
31c7349f90 Rewrite PTP clock CDC module for improved performance and timing closure at 25G 2021-03-30 15:57:46 -07:00
Alex Forencich
00d69a341c Test with sample clock on and off 2021-03-27 14:44:36 -07:00