FPGA/verilog-ethernet
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14 Commits

Author SHA1 Message Date
Alex Forencich
009560f583 Use latest version of cocotbext-eth 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-07 12:18:46 -08:00
Alex Forencich
f9ae6da8bd Improve PTP CDC module testbench 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-23 14:33:14 -07:00
Alex Forencich
aad30d09a1 Make FNS_WIDTH an internal parameter in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-21 16:30:29 -07:00
Alex Forencich
98b4fbb56d Remove USE_SAMPLE_CLOCK parameter in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-18 16:58:02 -07:00
Alex Forencich
c65161e696 Remove recursively-expanded macros for module parameters in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-17 16:04:16 -08:00
Alex Forencich
ab0c382123 Rework parameter handling in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-29 21:03:16 -08:00
Alex Forencich
6f2d581d62 Add output pipeline to PTP clock CDC module 2022-03-27 23:47:14 -07:00
Alex Forencich
23fb9d0bd8 Remove deprecated assignments 2022-03-16 18:43:36 -07:00
Alex Forencich
1f80696b55 Use start_soon instead of fork 2021-12-10 18:19:11 -08:00
Alex Forencich
31c7349f90 Rewrite PTP clock CDC module for improved performance and timing closure at 25G 2021-03-30 15:57:46 -07:00
Alex Forencich
00d69a341c Test with sample clock on and off 2021-03-27 14:44:36 -07:00
Alex Forencich
55359c1755 Report difference in ns 2021-03-27 14:44:21 -07:00
Alex Forencich
3cbe4b04da Improve timestamp difference measurement 2021-03-27 14:38:35 -07:00
Alex Forencich
8e1ad2eba6 Add cocotb testbench for ptp_clock_cdc 2020-12-29 22:55:55 -08:00