FPGA/verilog-ethernet
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2 Commits

Author SHA1 Message Date
Alex Forencich
4e49dbcf3d Pass parameters to model 2019-07-18 22:51:54 -07:00
Alex Forencich
cc1ff34f53 Add 64 bit timestamp support to ptp_clock_cdc 2019-07-15 16:36:02 -07:00