FPGA/verilog-ethernet
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7 Commits

Author SHA1 Message Date
Alex Forencich
8fea20ef77 Fix frame_ptr_reg width 2015-05-12 16:57:14 -07:00
Alex Forencich
51b5335318 Remove z from default states for FSM inference 2015-03-09 02:38:39 -07:00
Alex Forencich
867b799ecd Rework IP datapath modules to separate output register 2014-10-28 01:00:52 -07:00
Alex Forencich
c9a2b89717 Remove unused register 2014-09-24 01:12:48 -07:00
Alex Forencich
c74d2d1127 Update comment 2014-09-21 15:55:02 -07:00
Alex Forencich
119958cccb Remove unused parameter 2014-09-21 15:54:54 -07:00
Alex Forencich
4bee0542b7 Add IP modules (8 bit datapath) 2014-09-19 17:35:51 -07:00