FPGA/verilog-ethernet
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10 Commits

Author SHA1 Message Date
Alex Forencich
013e88253e Testbench updates 2019-03-07 23:44:43 -08:00
Alex Forencich
d2fedc4134 Rename ports 2018-11-07 22:35:06 -08:00
Alex Forencich
2e9602b5b4 Update testbenches to use wait 2018-07-02 18:20:07 -07:00
Alex Forencich
e4672915e6 Update testbenches to use instances() 2018-06-13 22:43:11 -07:00
Alex Forencich
0fd157964a Happy new year 2018-02-26 12:50:51 -08:00
Alex Forencich
9b2ac9dfc1 Happy new year 2017-05-18 13:47:45 -07:00
Alex Forencich
88150c9d5f Update and rework endpoints, update testbenches 2016-09-13 15:24:02 -07:00
Alex Forencich
9c01e114b4 Happy new year 2016-01-05 00:34:32 -08:00
Alex Forencich
5a4b480c7e Update testbenches for python 3 2015-03-21 22:31:01 -07:00
Alex Forencich
1acf493e9d Add 64 bit UDP transmit and receive modules 2014-09-25 17:28:05 -07:00