FPGA/verilog-ethernet
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3 Commits

Author SHA1 Message Date
Alex Forencich
079d6329cb Migrate example design testbenches to cocotb 2020-12-28 01:11:03 -08:00
Alex Forencich
a78627343d Change default target parameter 2020-12-25 01:48:24 -08:00
Alex Forencich
3b06f86dcf Add C10LP example design 2020-07-10 15:32:39 -07:00