FPGA/verilog-ethernet
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4 Commits

Author SHA1 Message Date
Alex Forencich
0ca8c9a59b Update example design timing constraints 2019-03-28 17:59:30 -07:00
Alex Forencich
cd6b87e984 Enable bitstream compression in example designs 2019-02-06 21:25:30 -08:00
Alex Forencich
3b47b422fa Fix Vivado clock groups 2016-10-06 17:52:23 -07:00
Alex Forencich
cbf1df718a Add example design for Digilent Nexys Video board 2016-06-29 12:00:05 -07:00