FPGA/verilog-ethernet
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102 Commits 1 Branch 0 Tags
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10 Commits

Author SHA1 Message Date
Alex Forencich
0d22a35bd8 Update output registers, remove extraneous resets, fix constant widths 2015-11-08 23:05:38 -08:00
Alex Forencich
7ea566e6d2 Update generate scripts to use argparse 2015-10-19 19:15:38 -07:00
Alex Forencich
ca11618e6d Convert to synchronous resets 2015-10-08 11:26:32 -07:00
Alex Forencich
26b165227c Update for compatibility with older versions of Python 2015-07-14 08:27:49 -07:00
Alex Forencich
04e4ccc517 Update for compatibility with older version of Python 2015-07-09 11:25:49 -07:00
Alex Forencich
b07c2d63b0 Parametrize tag and counter widths 2014-11-19 23:06:43 -08:00
Alex Forencich
789c7da6d6 Fix parameter 2014-11-13 10:39:41 -08:00
Alex Forencich
af0dce33b1 Separate out input mux in AXI frame joiner 2014-10-28 01:55:42 -07:00
Alex Forencich
a2a509884e Improve output register filling 2014-10-22 15:10:21 -07:00
Alex Forencich
7c3adb6c2b Add AXI stream frame joiner, generator, and testbench 2014-10-22 10:47:03 -07:00