FPGA/verilog-ethernet
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5 Commits

Author SHA1 Message Date
Alex Forencich
0d22a35bd8 Update output registers, remove extraneous resets, fix constant widths 2015-11-08 23:05:38 -08:00
Alex Forencich
ca11618e6d Convert to synchronous resets 2015-10-08 11:26:32 -07:00
Alex Forencich
b123525597 Add enable signal 2014-11-16 01:38:20 -08:00
Alex Forencich
7c86999399 Minor reorganization 2014-11-13 16:26:07 -08:00
Alex Forencich
5af6dc3501 Add AXI stream mux and testbench 2014-11-12 15:49:07 -08:00