FPGA/verilog-ethernet
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3 Commits

Author SHA1 Message Date
Alex Forencich
0d22a35bd8 Update output registers, remove extraneous resets, fix constant widths 2015-11-08 23:05:38 -08:00
Alex Forencich
ca11618e6d Convert to synchronous resets 2015-10-08 11:26:32 -07:00
Alex Forencich
87fe1a561f Add AXI stream tap modules 2015-06-22 14:56:56 -07:00