FPGA/verilog-ethernet
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6 Commits

Author SHA1 Message Date
Alex Forencich
c65161e696 Remove recursively-expanded macros for module parameters in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-17 16:04:16 -08:00
Alex Forencich
57803eeeb8 Remove deprecated assignments 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-24 15:07:45 -08:00
Alex Forencich
1f80696b55 Use start_soon instead of fork 2021-12-10 18:19:11 -08:00
Alex Forencich
77d22bfde0 Rework sim_build output directory, fix default makefile target 2020-12-29 14:47:12 -08:00
Alex Forencich
0359d8d76a Use absolute path to test directory 2020-12-28 19:25:59 -08:00
Alex Forencich
079d6329cb Migrate example design testbenches to cocotb 2020-12-28 01:11:03 -08:00