FPGA/verilog-ethernet
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2 Commits

Author SHA1 Message Date
Alex Forencich
0be84e3b03 Write to _next instead of _reg in async block 2015-05-04 01:17:39 -07:00
Alex Forencich
db6a6e23f5 Add 64 bit Ethernet FCS checker 2015-03-22 01:05:57 -07:00