FPGA/verilog-ethernet
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3 Commits

Author SHA1 Message Date
Alex Forencich
455ddf5df2 Fix error detect in 10G MAC 2015-06-06 00:49:40 -07:00
Alex Forencich
0352d55084 Add default case 2015-05-16 22:34:29 -07:00
Alex Forencich
bf349b16ba Add 10G MAC module 2015-05-08 00:05:21 -07:00