FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-28 07:03:08 +08:00
Code Issues Projects Releases Wiki Activity
956 Commits 1 Branch 0 Tags
Commit Graph

8 Commits

Author SHA1 Message Date
Alex Forencich
0f2478d68c Fix wires 2021-10-20 17:21:16 -07:00
Alex Forencich
a78627343d Change default target parameter 2020-12-25 01:48:24 -08:00
Alex Forencich
fd908dd2aa Clean up clock connections 2020-08-06 17:15:38 -07:00
Alex Forencich
27ed447005 Use common sync_reset module files 2020-03-27 18:27:45 -07:00
Alex Forencich
c5e886769a Fix typo 2019-07-19 10:29:55 -07:00
Alex Forencich
16e5ec2106 Update example designs 2019-07-18 17:13:47 -07:00
Alex Forencich
978fdce95c Minor fixes 2019-04-03 20:57:10 -07:00
Alex Forencich
0008956828 Add Arty example design 2019-03-28 19:38:55 -07:00