FPGA/verilog-ethernet
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3 Commits

Author SHA1 Message Date
Alex Forencich
0f2478d68c Fix wires 2021-10-20 17:21:16 -07:00
Alex Forencich
0b41dc4011 Rework GT instances in ZCU102 design 2021-10-19 18:38:22 -07:00
Alex Forencich
9a8ba2f0f2 Add ZCU102 example design 2020-09-18 00:15:21 -07:00