FPGA/verilog-ethernet
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2 Commits

Author SHA1 Message Date
Alex Forencich
3063a761e5 Support both versions of ML605 2018-02-26 00:18:14 -08:00
Alex Forencich
cf6a01fffe Add ML605 SGMII design 2017-07-22 11:07:23 -07:00