FPGA/verilog-ethernet
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3 Commits

Author SHA1 Message Date
Alex Forencich
0fd157964a Happy new year 2018-02-26 12:50:51 -08:00
Alex Forencich
9b2ac9dfc1 Happy new year 2017-05-18 13:47:45 -07:00
Alex Forencich
0b6614e8d4 Add UDP checksum generator modules and testbenches 2016-09-30 21:59:04 -07:00