FPGA/verilog-ethernet
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309 Commits 1 Branch 0 Tags
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6 Commits

Author SHA1 Message Date
Alex Forencich
150d5ad04e Handle out-of-range select as drop 2021-11-24 14:58:16 -08:00
Alex Forencich
2972a1fa81 Add default_nettype none and resetall directives 2021-10-20 15:33:38 -07:00
Alex Forencich
c5f44c70d1 Add parameter documentation 2019-07-24 13:54:21 -07:00
Alex Forencich
b1f3a74b86 Remove unused code 2019-03-07 22:59:15 -08:00
Alex Forencich
cadd1bcb50 Match width 2018-12-09 00:04:30 -08:00
Alex Forencich
9d813226d0 Convert generated demux to verilog parametrized demux 2018-10-24 22:16:05 -07:00