FPGA/verilog-ethernet
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692 Commits 1 Branch 0 Tags
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10 Commits

Author SHA1 Message Date
Alex Forencich
16e5ec2106 Update example designs 2019-07-18 17:13:47 -07:00
Alex Forencich
d62a5ad050 Fix quotes 2019-06-27 01:26:58 -07:00
Alex Forencich
dfafa9c83d Update vivado.mk 2019-06-27 00:59:36 -07:00
Alex Forencich
025f05e667 Add nojournal and nolog 2019-06-27 00:48:20 -07:00
Alex Forencich
af4f675840 Fix for dash 2019-06-27 00:15:36 -07:00
Alex Forencich
dc4416a261 Update Arty flash programming commands 2019-06-26 19:00:20 -07:00
Alex Forencich
d166350d77 Update Arty XDC 2019-06-26 18:59:41 -07:00
Alex Forencich
352f52e159 Add flash target to Arty example design 2019-05-27 01:02:55 -07:00
Alex Forencich
978fdce95c Minor fixes 2019-04-03 20:57:10 -07:00
Alex Forencich
0008956828 Add Arty example design 2019-03-28 19:38:55 -07:00