FPGA/verilog-ethernet
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7 Commits

Author SHA1 Message Date
Alex Forencich
aebe0549dd Happy new year 2017-05-18 13:35:11 -07:00
Alex Forencich
52fc34d82e Assume first tkeep bit is always set 2016-07-20 12:36:59 -07:00
Alex Forencich
be4034071b Happy new year 2016-01-05 00:24:20 -08:00
Alex Forencich
0d22a35bd8 Update output registers, remove extraneous resets, fix constant widths 2015-11-08 23:05:38 -08:00
Alex Forencich
dcad442e7c Improve timing performance of frame length adjust module 2015-10-19 00:30:50 -07:00
Alex Forencich
ca11618e6d Convert to synchronous resets 2015-10-08 11:26:32 -07:00
Alex Forencich
c15761068a Add AXI stream frame length adjust modules 2015-06-05 17:04:10 -07:00