FPGA/verilog-ethernet
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8 Commits

Author SHA1 Message Date
Alex Forencich
a98dfce099 Update output registers, remove extraneous resets, fix constant widths 2015-11-09 23:50:34 -08:00
Alex Forencich
cc5fead04d Convert to synchronous resets 2015-10-09 22:36:58 -07:00
Alex Forencich
51b5335318 Remove z from default states for FSM inference 2015-03-09 02:38:39 -07:00
Alex Forencich
0f62d31fef Rework ARP datapath modules to separate output register 2014-10-28 01:55:36 -07:00
Alex Forencich
2fd2663eee Update comments 2014-09-19 17:31:34 -07:00
Alex Forencich
33c044e035 Add invalid header and tuser assert checks and tests 2014-09-15 19:31:10 -07:00
Alex Forencich
85d11645eb Rename frame_error to error_header_early_termination 2014-09-15 19:08:01 -07:00
Alex Forencich
ea2b1b99d0 Add ARP frame to Ethernet frame modules 2014-09-15 19:06:02 -07:00