FPGA/verilog-ethernet
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6 Commits

Author SHA1 Message Date
Alex Forencich
a98dfce099 Update output registers, remove extraneous resets, fix constant widths 2015-11-09 23:50:34 -08:00
Alex Forencich
08afe3a5d2 Synchronize MAC status signals 2015-10-09 22:51:55 -07:00
Alex Forencich
55071645fd Update async FIFO instances 2015-10-09 22:35:25 -07:00
Alex Forencich
0ecd354d7f Fix instance name 2015-06-07 22:07:04 -07:00
Alex Forencich
ec95a6055d Feed through and synchronize FIFO status signals 2015-05-12 19:12:23 -07:00
Alex Forencich
00a87b26b3 Add FIFO wrapper for 10G MAC module 2015-05-08 00:07:09 -07:00