FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-28 07:03:08 +08:00
Code Issues Projects Releases Wiki Activity
292 Commits 1 Branch 0 Tags
Commit Graph

3 Commits

Author SHA1 Message Date
Alex Forencich
a98dfce099 Update output registers, remove extraneous resets, fix constant widths 2015-11-09 23:50:34 -08:00
Alex Forencich
73e0a1cff4 Fail outgoing frames on tvalid deassert 2015-10-20 16:05:23 -07:00
Alex Forencich
6dee616834 Add gigabit MAC module 2015-02-26 19:16:08 -08:00