FPGA/verilog-ethernet
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375 Commits 1 Branch 0 Tags
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5 Commits

Author SHA1 Message Date
Alex Forencich
1b6816b06f Add ML605 RGMII example design 2017-05-31 20:24:43 -07:00
Alex Forencich
de00b3e233 Rename ML605 example design 2017-05-31 20:06:32 -07:00
Alex Forencich
e376c805d2 Update ML605 reference design 2017-05-31 19:52:43 -07:00
Alex Forencich
0fc986041e Fix example design LED logic 2017-05-19 17:44:29 -07:00
Alex Forencich
57a16b7d54 Add ML605 example design 2017-05-19 17:33:07 -07:00