FPGA/verilog-ethernet
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6 Commits

Author SHA1 Message Date
Alex Forencich
0e26b3a8a4 Put back lane shifting logic 2014-10-28 00:54:15 -07:00
Alex Forencich
205be7ed27 Rework AXI ethernet modules to separate output register 2014-10-23 00:05:06 -07:00
Alex Forencich
d7f30a777b Update comments 2014-09-15 19:05:18 -07:00
Alex Forencich
a8958f4b23 Remove unnecessary registers 2014-09-15 19:04:49 -07:00
Alex Forencich
46c29160ff Wait for header instead of payload 2014-09-15 19:03:31 -07:00
Alex Forencich
8e4d162667 Add ethernet frame to AXI stream modules 2014-09-14 01:06:48 -07:00