FPGA/verilog-ethernet
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837 Commits 1 Branch 0 Tags
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8 Commits

Author SHA1 Message Date
Alex Forencich
c0c2dbce2a Update XDC files 2021-02-06 15:15:34 -08:00
Alex Forencich
77d22bfde0 Rework sim_build output directory, fix default makefile target 2020-12-29 14:47:12 -08:00
Alex Forencich
0359d8d76a Use absolute path to test directory 2020-12-28 19:25:59 -08:00
Alex Forencich
079d6329cb Migrate example design testbenches to cocotb 2020-12-28 01:11:03 -08:00
Alex Forencich
bf9f1a6211 Update flash programming commands 2020-09-29 18:29:27 -07:00
Alex Forencich
6aba3a741a Update makefiles 2020-08-06 17:19:11 -07:00
Alex Forencich
fd908dd2aa Clean up clock connections 2020-08-06 17:15:38 -07:00
Alex Forencich
f0e130aa48 Add AU50 10G example design 2020-07-17 00:06:32 -07:00