FPGA/verilog-ethernet
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3 Commits

Author SHA1 Message Date
Alex Forencich
cf832f581c Set algorithm for pytest-split 2021-06-28 01:34:34 -07:00
Alex Forencich
eeb04acdd0 Update github actions 2021-01-16 13:39:56 -08:00
Alex Forencich
731fd859ac Add Github Actions regression tests 2020-12-28 20:19:58 -08:00