FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-02-04 07:13:13 +08:00
Code Issues Projects Releases Wiki Activity
1,122 Commits 1 Branch 0 Tags
Commit Graph

7 Commits

Author SHA1 Message Date
Alex Forencich
20c542051d Use cfg prefix for configuration signals 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-22 17:14:52 -07:00
Alex Forencich
6b18e56cb1 Add default_nettype none and resetall directives 2021-10-20 17:29:12 -07:00
Alex Forencich
52d8867f73 Use BUFG instead of BUFIO2 for DDR input on Spartan 6 2021-07-31 12:45:38 -07:00
Alex Forencich
edcfd0dc40 Prevent SRL inference in synchronizers 2019-03-28 12:36:32 -07:00
Alex Forencich
585ccefa15 Add TX underflow error signal 2019-03-26 12:42:08 -07:00
Alex Forencich
0fd157964a Happy new year 2018-02-26 12:50:51 -08:00
Alex Forencich
a3b5d5d167 Update RGMII PHY interface and add RGMII MAC wrappers 2017-05-31 18:40:49 -07:00