FPGA/verilog-ethernet
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5 Commits

Author SHA1 Message Date
Alex Forencich
b4d09cbbdf More extensive overhaul of the PTP period output module to improve resource consumption and parallelize computation 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-16 17:01:03 -08:00
Alex Forencich
f313fafc70 Separate locked status from fast-forward mode in PTP period output module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2024-01-15 22:55:50 -08:00
Alex Forencich
6b18e56cb1 Add default_nettype none and resetall directives 2021-10-20 17:29:12 -07:00
Alex Forencich
42950abf12 Refactor PTP period output, implement error output 2021-03-30 15:25:34 -07:00
Alex Forencich
fdfb517761 Add PTP perout module and testbench 2019-06-27 01:30:18 -07:00