FPGA/verilog-ethernet
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2 Commits

Author SHA1 Message Date
Alex Forencich
2bc052e0d5 Update LED driver timing constraints 2020-09-28 17:24:11 -07:00
Alex Forencich
6a4bcaab38 Add timing constraints for LED driver 2020-09-22 22:13:59 -07:00