FPGA/verilog-ethernet
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4 Commits

Author SHA1 Message Date
Alex Forencich
0fd157964a Happy new year 2018-02-26 12:50:51 -08:00
Alex Forencich
9a507b388d Update LFSR module 2017-06-09 21:17:28 -07:00
Alex Forencich
9b2ac9dfc1 Happy new year 2017-05-18 13:47:45 -07:00
Alex Forencich
ccd8cd8c2e Add generic LFSR module 2016-06-28 17:25:09 -07:00