FPGA/verilog-ethernet
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930 Commits 1 Branch 0 Tags
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7 Commits

Author SHA1 Message Date
Alex Forencich
2796e681c9 Prevent latch inference 2021-03-30 22:23:40 -07:00
Alex Forencich
31c7349f90 Rewrite PTP clock CDC module for improved performance and timing closure at 25G 2021-03-30 15:57:46 -07:00
Alex Forencich
b26f923c2f Reset synchronizers 2019-07-18 18:35:30 -07:00
Alex Forencich
adb9c4d147 Fix initial values 2019-07-18 18:35:11 -07:00
Alex Forencich
cc1ff34f53 Add 64 bit timestamp support to ptp_clock_cdc 2019-07-15 16:36:02 -07:00
Alex Forencich
31cb54e67e Make old icarus verilog happy 2019-07-15 16:15:50 -07:00
Alex Forencich
77bae7a77e Add PTP clock CDC module and testbench 2019-07-15 15:16:17 -07:00