FPGA/verilog-ethernet
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6 Commits

Author SHA1 Message Date
Alex Forencich
6b4dd02946 Resolve multiple driver issue 2015-02-28 00:43:27 -08:00
Alex Forencich
867b799ecd Rework IP datapath modules to separate output register 2014-10-28 01:00:52 -07:00
Alex Forencich
8191b38e7a Move header valid assign to top 2014-09-25 16:25:37 -07:00
Alex Forencich
5eaba1c3b3 Do not clock out a header if the last signal falls on the last word 2014-09-24 23:52:41 -07:00
Alex Forencich
119958cccb Remove unused parameter 2014-09-21 15:54:54 -07:00
Alex Forencich
4bee0542b7 Add IP modules (8 bit datapath) 2014-09-19 17:35:51 -07:00