FPGA/verilog-ethernet
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2 Commits

Author SHA1 Message Date
Alex Forencich
0927f4c326 Fix readme 2019-06-19 23:51:04 -07:00
Alex Forencich
1eb9c39ed3 Add VCU118 25G example design 2019-06-19 23:25:06 -07:00