FPGA/verilog-ethernet
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Commit Graph

311 Commits

Author SHA1 Message Date
Alex Forencich
eb1f38a749 More critical path optimizations 2019-06-19 15:06:55 -07:00
Alex Forencich
134ce04777 Add configurable serdes pipeline register chain 2019-06-19 00:57:28 -07:00
Alex Forencich
303dec8165 Sum errors across data and header 2019-06-19 00:25:41 -07:00
Alex Forencich
1d3554c37e Rework pointer handling to improve timing 2019-06-16 23:53:26 -07:00
Alex Forencich
7ec836baf6 IP header checksum optimizations 2019-06-16 22:01:11 -07:00
Alex Forencich
b17966f73d store_last_word timing optimization 2019-06-16 20:01:08 -07:00
Alex Forencich
55bf44117b shift_axis_extra_cycle timing optimization 2019-06-16 19:57:52 -07:00
Alex Forencich
3b959b2765 CRC handling logic optimizations 2019-06-16 17:39:28 -07:00
Alex Forencich
320a45c4ab Remove unused state bit 2019-06-16 17:33:14 -07:00
Alex Forencich
8bb243cd35 MAC termination detect timing optimizations 2019-06-16 15:44:41 -07:00
Alex Forencich
4f97303e44 Remove unused code 2019-06-16 15:38:35 -07:00
Alex Forencich
938479c246 MAC RX timing optimizations 2019-06-16 00:36:50 -07:00
Alex Forencich
3684ccafb2 Make use of blocking statements consistent 2019-06-15 16:56:45 -07:00
Alex Forencich
ce13522085 Implement ARP cache clear 2019-06-14 00:01:13 -07:00
Alex Forencich
b41ab00381 Initialize ARP cache 2019-06-13 23:45:17 -07:00
Alex Forencich
296744b37e Make use of blocking statements consistent 2019-06-12 23:31:03 -07:00
Alex Forencich
6eff2f0030 Decouple transmit PTP tag enable and transmit PTP timestamp enable 2019-06-09 22:03:24 -07:00
Alex Forencich
2794c315e8 Fix synthesizer complaints 2019-06-08 17:36:09 -07:00
Alex Forencich
82fe5a6bdd Add PTP timestamp capture logic to MACs 2019-06-07 16:38:36 -07:00
Alex Forencich
659aa67481 Pack start packet strobes into the same signal 2019-06-06 17:13:14 -07:00
Alex Forencich
e181ea5abc Add PTP clock module and testbench 2019-06-03 19:00:28 -07:00
Alex Forencich
3da3725429 Disable bit slipping when RX PRBS check is enabled 2019-05-16 23:22:47 -07:00
Alex Forencich
79ec137243 Add PRBS31 generation and checking to 10G PHY 2019-05-10 20:28:45 -07:00
Alex Forencich
b7d297850c Move 10G PHY interface logic into separate modules 2019-05-10 14:56:18 -07:00
Alex Forencich
696c634726 Add rx_bad_block outputs 2019-04-17 00:16:45 -07:00
Alex Forencich
1bec485766 Fix constants 2019-04-03 11:48:09 -07:00
Alex Forencich
8e2d936884 Add MII PHY interface, MAC wrappers, and testbenches 2019-03-28 19:18:03 -07:00
Alex Forencich
8285f94eaa Rename tx_sync regs 2019-03-28 16:27:33 -07:00
Alex Forencich
3eaed305f5 Connect TX underflow status outputs 2019-03-28 16:27:15 -07:00
Alex Forencich
edcfd0dc40 Prevent SRL inference in synchronizers 2019-03-28 12:36:32 -07:00
Alex Forencich
585ccefa15 Add TX underflow error signal 2019-03-26 12:42:08 -07:00
Alex Forencich
b691a30760 Accept OS_START block type 2019-03-26 12:06:58 -07:00
Alex Forencich
9891d75c2f Fix STATE_WAIT_END 2019-03-25 23:24:01 -07:00
Alex Forencich
0efb135b7a Fix STATE_WAIT_END 2019-03-25 15:06:45 -07:00
Alex Forencich
fb4abb6b39 Fix widths 2019-03-14 14:44:00 -07:00
Alex Forencich
ec38440d89 Add 10G Ethernet MAC/PHY combination modules and testbenches 2019-01-31 18:13:07 -08:00
Alex Forencich
e644ce3895 Add start packet strobe timing outputs to MAC modules 2019-01-31 17:00:23 -08:00
Alex Forencich
9ae60dcd9a Simplify lane swapping code 2019-01-22 14:22:01 -08:00
Alex Forencich
54e31c51b7 Adjustment to scrambler bypass 2019-01-22 14:21:14 -08:00
Alex Forencich
6238ed5755 Report error for invalid encoding 2019-01-22 14:19:43 -08:00
Alex Forencich
e784900050 Remove unused code 2019-01-22 14:18:27 -08:00
Alex Forencich
dbbbc28059 Add 10G Ethernet PHY modules and testbenches 2019-01-16 18:00:56 -08:00
Alex Forencich
91553e6edf Add XGMII 10GBASE-R encoder and decoder modules and testbenches 2019-01-16 17:30:07 -08:00
Alex Forencich
ea02b6c898 Properly handle short IFG 2019-01-16 13:26:47 -08:00
Alex Forencich
32d889b20d Remove unreachable code 2019-01-16 13:26:14 -08:00
Alex Forencich
6b85aed564 Any control characters in packet considered an error 2018-11-08 13:34:32 -08:00
Alex Forencich
ebe31e811c Use parameters for control characters 2018-11-08 13:15:47 -08:00
Alex Forencich
6b1b36ded6 Assert header ready earlier if possible 2018-11-07 23:10:07 -08:00
Alex Forencich
b223c94adb Use registered header 2018-11-07 23:08:40 -08:00
Alex Forencich
d2fedc4134 Rename ports 2018-11-07 22:35:06 -08:00