FPGA/verilog-ethernet
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2 Commits

Author SHA1 Message Date
Alex Forencich
4f1eabab17 Split async FIFO resets 2021-10-13 14:05:13 -07:00
Alex Forencich
b7f3faa628 Add timing constraints for Quartus Prime Pro 2021-05-18 16:02:36 -07:00