FPGA/verilog-ethernet
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6 Commits

Author SHA1 Message Date
Alex Forencich
e0f740457b Testbench updates 2019-03-07 22:51:40 -08:00
Alex Forencich
9d813226d0 Convert generated demux to verilog parametrized demux 2018-10-24 22:16:05 -07:00
Alex Forencich
3063bba54b Update testbenches to use wait 2018-07-02 16:19:35 -07:00
Alex Forencich
c5837daa2f Update testbenches to use instances() 2018-06-13 22:26:10 -07:00
Alex Forencich
5df7efe516 Happy new year 2018-02-26 12:25:20 -08:00
Alex Forencich
57e700f802 Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream demux 2017-11-20 20:14:20 -08:00