FPGA/verilog-ethernet
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5 Commits

Author SHA1 Message Date
Alex Forencich
306c0ea590 Rework mux logic 2016-08-29 19:25:43 -07:00
Alex Forencich
9c01e114b4 Happy new year 2016-01-05 00:34:32 -08:00
Alex Forencich
a98dfce099 Update output registers, remove extraneous resets, fix constant widths 2015-11-09 23:50:34 -08:00
Alex Forencich
cc5fead04d Convert to synchronous resets 2015-10-09 22:36:58 -07:00
Alex Forencich
4db581ae3c Add ethernet demux module and testbench 2014-11-17 21:52:49 -08:00