FPGA/verilog-ethernet
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6 Commits

Author SHA1 Message Date
Alex Forencich
7751aba8da Reorganize timing constraints 2021-05-18 16:15:41 -07:00
Alex Forencich
27ed447005 Use common sync_reset module files 2020-03-27 18:27:45 -07:00
Alex Forencich
16e5ec2106 Update example designs 2019-07-18 17:13:47 -07:00
Alex Forencich
025f05e667 Add nojournal and nolog 2019-06-27 00:48:20 -07:00
Alex Forencich
15b3aaf2e7 Update programming commands 2019-06-26 20:17:45 -07:00
Alex Forencich
1d61626785 Add KC705 GMII example design 2019-05-02 19:29:47 -07:00