FPGA/verilog-ethernet
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2 Commits

Author SHA1 Message Date
Alex Forencich
6b18e56cb1 Add default_nettype none and resetall directives 2021-10-20 17:29:12 -07:00
Alex Forencich
a91e2b7e17 Add KC705 SGMII example design 2020-12-30 17:15:34 -08:00