FPGA/verilog-ethernet
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12 Commits

Author SHA1 Message Date
Alex Forencich
3b959b2765 CRC handling logic optimizations 2019-06-16 17:39:28 -07:00
Alex Forencich
320a45c4ab Remove unused state bit 2019-06-16 17:33:14 -07:00
Alex Forencich
8bb243cd35 MAC termination detect timing optimizations 2019-06-16 15:44:41 -07:00
Alex Forencich
4f97303e44 Remove unused code 2019-06-16 15:38:35 -07:00
Alex Forencich
938479c246 MAC RX timing optimizations 2019-06-16 00:36:50 -07:00
Alex Forencich
82fe5a6bdd Add PTP timestamp capture logic to MACs 2019-06-07 16:38:36 -07:00
Alex Forencich
e644ce3895 Add start packet strobe timing outputs to MAC modules 2019-01-31 17:00:23 -08:00
Alex Forencich
32d889b20d Remove unreachable code 2019-01-16 13:26:14 -08:00
Alex Forencich
6b85aed564 Any control characters in packet considered an error 2018-11-08 13:34:32 -08:00
Alex Forencich
ebe31e811c Use parameters for control characters 2018-11-08 13:15:47 -08:00
Alex Forencich
d2fedc4134 Rename ports 2018-11-07 22:35:06 -08:00
Alex Forencich
de69975872 Add AXI stream XGMII RX and TX modules and testbenches 2018-10-23 23:34:43 -07:00